Power management masked clock circuitry, systems and methods

Claims

What is claimed is:

1. An electronic system comprising:

a register for duty cycle data; and

a clock circuit coupled to said register, said clock circuit comprising first circuitry and second circuitry wherein said first circuitry provides a first circuitry signal and said second circuitry combines said duty cycle data and said first circuitry signal into a second circuitry signal having a duty cycle defined by said duty cycle data and a frequency defined by said first circuitry signal.

2. The electronic system of claim 1 further comprising a modulating circuit wherein said clock circuit supplies a digital masking signal, and said modulating circuit modulates a clock signal with said digital masking signal.

3. The electronic system of claim 2 further comprising a microprocessor wherein said modulating circuit is integrated with said microprocessor onto one integrated circuit chip.

4. The electronic system of claim 2 wherein said register and clock circuit are integrated onto one integrated circuit chip.

5. The electronic system of claim 2 further comprising:

a power management circuit having an output representing the presence or absence of a standby state; and

a logic circuit coupled to the output of said power management circuit to produce a single logic level to said second part of said clock circuit when the output of said power management circuit represents that said standby state is absent, and to pass said digital masking signal from said first part of said clock circuit to said second part of said clock circuit when the output of said power management circuit represents that said standby state is present.

6. The electronic system of claim 1 wherein said duty cycle data provides 2.sup.n possible duty cycle selections where n equals the number of bits in said register.

7. The electronic system of claim 1 wherein said second circuitry signal is combined with a clock signal to generate a series of clock pulses occupying time intervals wherein said series of clock pulses is followed by time intervals free of clock pulses such that the ratio of the time intervals of said series of clock pulses and said time intervals free of clock pulses is responsive to said duty cycle data.

8. The electronic system of claim 7 further comprising a microprocessor coupled to receive the series of clock pulses to clock the microprocessor.

9. The electronic system of claim 1 wherein said first circuitry comprises a counter having a multibit output.

10. The electronic system of claim 9 wherein said first circuitry signal is said multibit output of said counter.

11. The electronic system of claim 9 wherein said second circuitry further comprises:

a comparator having a first multibit input coupled to receive said duty cycle data from said register and a second multibit input coupled to receive said multi-bit output of said counter.

12. The electronic system of claim 9 further comprising a clock rate circuit to provide a clock signal to said counter.

13. The electronic system of claim 12 wherein the frequency of said clock signal is programmable.

14. The electronic system of claim 12 further comprising:

a system management interrupt (SMI) circuit having a periodic SMI signal source and providing a periodic SMI control signal representing the presence or absence of said periodic SMI signal from said source wherein said clock rate circuit is responsive to said periodic SMI control signal to gate either said periodic SMI source or a predetermined clock to said counter depending on the state of said periodic SMI control signal.

15. The electronic system of claim 12 wherein said frequency is defined by said clock signal.

16. An electronic device comprising:

a register for duty cycle data;

a clock circuit, coupled to said register, comprising first circuitry and second circuitry wherein said first circuitry provides a first circuitry signal and said second circuitry combines said duty cycle data and said first circuitry signal into a second circuitry signal having a duty cycle defined by said duty cycle data and a frequency defined by said first circuitry signal.

17. The electronic device of claim 16 wherein said duty cycle data provides 2.sup.n possible duty cycle selections where n equals the number of bits in said register.

18. The electronic device of claim 16 wherein said second circuitry signal is combined with a clock signal to generate a series of clock pulses occupying time intervals wherein said series of clock pulses is followed by time intervals free of clock pulses such that the ratio of the time intervals of said series of clock pulses and said time intervals free of clock pulses is responsive to said duty cycle data.

19. The electronic device of claim 16 wherein said first circuitry comprises a counter having a multibit output.

20. The electronic device of claim 19 wherein said first circuits signal is said multibit output of said counter.

21. The electronic device of claim 19 wherein said second circuitry further comprises:

a comparator having a first multibit input connected to receive said duty cycle data from said register and a second multibit input connected to receive said multi-bit output of said counter.

22. The electronic device of claim 19 furt