An interconnect forming method includes the steps of: a) forming a through hole in an insulating film over a substrate; b) depositing a photosensitive masking material over the insulating film as well as inside the hole; c) patterning the material, thereby forming a mask pattern, which has an opening located over the hole and is used to define a trench; d) etching the insulating film to a predetermined depth using the mask pattern, thereby defining a trench pattern, linked to the hole, in an upper part of the insulating film; e) filling in the hole and the trench pattern with a conductive material; and f) before the trench pattern is defined, defining the mask pattern so that no remaining part of the material, which has been filled in the hole, will reach a level higher than the bottom of the trench pattern.

An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a conductive structure over the substrate, the conductive structure comprised of an oxygen-sensitive conductor; forming a layer of dielectric material over the conductive structure (step 306 of FIG. 1); forming a photoresist layer over the layer of the dielectric material (step 308 of FIG. 1); patterning the layer of the dielectric material (step 308); removing the photoresist layer after patterning the layer of the dielectric material (step 312 of FIG. 1); and subjecting the semiconductor wafer to a plasma which incorporates the combination of hydrogen or deuterium and a fluorine-containing mixture which is comprised of a gas selected from the group consisting of: CF.sub.4, C.sub.2 F.sub.6, CHF.sub.3, CFH.sub.3 and other fluorine-containing hydrocarbon (step 313 of FIG. 1).

Described is a semiconductor device having a buried multilayer wiring structure, in which there is ensured good conductivity among a plurality of wiring layers. A lower wiring pattern is formed from conductive material, and an upper wiring pattern is formed from conductive material. Insulating layers are provided between the lower wiring pattern and the upper wiring pattern. A connection section is formed so as to penetrate through the insulating layers to thereby establish continuity between the lower and upper wiring patterns, as well as to have a greater cross-sectional area at the end facing the upper wiring pattern and a smaller cross-sectional area at the end facing the lower wiring pattern.

An apparatus, system and method for fabricating a wafer utilizing a dual damascene process are described. A wafer-in-process, having conductive plugs within a first dielectric layer, a hard mask over the first dielectric layer, vias in a second dielectric layer which overlies the hard mask, and a photoresist material within the vias is further processed by a photolithographic device having transparent portions and radiant energy inhibiting portions. The photolithographic device is registered to the wafer-in-process to prevent radiant energy from being directly transmitted into the photoresist material overlaying the vias. This prevents the exposure of a portion of the photoresist material at a lower portion of the vias, thus protecting the hard mask layer and/or the conductive plugs from damage during a subsequent etching process. The exposed photoresist material is then removed.

A semiconductor device has a wiring slot and two wiring layers connected by a via hole. The semiconductor device is formed using a photodegradable polymer film that degrades under UV radiation. An incidence angle .theta. of radiation rays in the irradiating step with respect to a perpendicular direction of a surface of the substrate, fulfills the relationship tan .theta..gtoreq.H+H'/2(D+D') wherein D is a depth of the wiring slot, D' is a thickness of the photoresist film, H is a diameter of the via hole in a opening of the wiring slot, and H' is the width of the wiring slot.