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Description  |
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BACKGROUND OF THE INVENTION
The present invention relates to three phase AC motor controllers and more
particularly, to an apparatus for altering stator winding voltages to
essential eliminate any overshoot voltage greater than a DC bus voltage
magnitude.
One type of commonly designed induction motor is a three phase motor having
three Y-connected stator windings. In this type of motor, each phase's
stator winding is connected to an AC voltage source by a separate
transmission line, the source generating currents therein. Often, an
adjustable speed drive (ASD) will be positioned between the voltage source
and the motor to control motor speed.
One commonly used type of ASD includes a PWM voltage source invertor (VSI).
PWM VSIs operate by converting a DC voltage into a series of high
frequency AC voltage pulses. PWM invertors can control the widths of the
positive and negative phase portions of each pulse, thus producing a
changing average voltage. All of the high frequency pulses are provided at
motor terminals and their changing average over a period defines a
fundamental low frequency alternating voltage at the terminals. The
amplitude of the fundamental voltage can be controlled by adjusting the
ratio of positive to negative phase portions of each high frequency pulse.
The frequency of the fundamental voltage can be controlled by altering the
period over which the average high frequency pulses alternate from
positive to negative phase. Depending upon its design, a given PWM can
produce a fundamental low frequency alternating voltage having a range of
different frequencies to drive a motor at many different speeds, hence the
term ASD.
Referring to FIG. 1, a transmission line 80 such as may be used as a supply
line to an AC motor can be represented by a ".pi." distributed equivalent
circuit per unit length of cable. The n distributed circuit includes a
plurality of inductors 81, resistors 71, and capacitors 82, the inductors
81 and resistors 82 arranged in series and the capacitors 71 arranged in
parallel, one capacitor 82 connecting a point between each resistor and
inductor pair to a "reference return" line 76. Looking back along supply
line 80 from a stator terminal 20, 21, or 22 toward a voltage source 15, a
supply line 80 will have a characteristic impedance Z.sub.0 in ohms equal
to
##EQU1##
where L is the line inductance 81 in Henrys per meter and C is the line
capacitance 82 in Farads per meter. As a high frequency voltage pulse
e.sup.+ emitted from the PWM VSI travels along the supply line 80, it
produces a current i.sup.+ =e.sup.+ /Z.sub.0.
The high frequency equivalent circuit of a stator winding 75, like a
transmission line, can also be represented by a n distributed equivalent
circuit made up of capacitors, inductances and resistors. This circuit
model is different from the standard low frequency (60 Hz) induction motor
model. Therefore, the stator winding 75 responding to the high frequency
voltage pulses also has a high frequency characteristic impedance Z.sub.t,
where the supply line is terminated. At termination it must be true that:
##EQU2##
where Total e is the voltage across the stator winding and Total i is the
current through the stator winding.
When high frequency voltage pulses are produced, unless Z.sub.t =Z.sub.0,
part of the incident wave e.sup.+ is reflected back toward the voltage
supply 15 thus producing a reflected voltage e.sup.-. The reflected
voltage e.sup.- and associated reflected current i.sup.- are related to
the line impedance by the equation i.sup.- =e.sup.- /Z.sub.0. At the
termination, Equation 1 can be rewritten as:
##EQU3##
where the subscript t refers to values at the point of termination at the
stator winding.
Equation .sub.2 can be rewritten in terms of Z.sub.0 as
##EQU4##
Solving Equation 3 for a ratio of reflected to incident voltage:
##EQU5##
where the ratio K is called the reflection co-efficient. K will be zero
and there will be no reflection at the termination only when the
terminating impedance Z.sub.t is equal to the characteristic impedance
Z.sub.0 of the line.
Often, when the terminating impedance Z.sub.t is different than the line
impedance Z.sub.0, the reflected waves e.sup.- and incident waves e.sup.+
combine to form standing waves or overvoltages having an amplitude that
can be as much as twice the amplitude of the incident wave, thus forming
an overvoltage surge at the motor terminals. Importantly, the stator high
frequency terminal impedance Z.sub.t is usually quite different and
several orders of magnitude greater than the line impedance Z.sub.0. Thus,
voltage surges having amplitudes which are twice the DC bus voltage
amplitude are a common phenomenon in the motor control industry.
Over voltage magnitude depends upon the characteristic motor termination
impedance Z.sub.t, cable impedance Z.sub.0, the cable length and the steep
front rise and fall times of the high frequency PWM pulses and may be
estimated using standard transmission line standing wave theory. The rise
time of the steep front high frequency PWM pulses is essentially fixed by
the VSI semiconductor device switching times and varies with device
technology as shown in Table I. An equivalent switch risetime frequency
(f.sub.u) and wavelength (.lambda.) of the traveling incident wave e.sup.+
may be defined using Equations (5) and (6) below.
##EQU6##
where c is the speed of light, and trise is the rise time associated with
the semiconductor device. A critical cable length equal to or greater than
.lambda./4 results in twice the amplitude of the incident wave at the
motor terminals when Z.sub.t >>Z.sub.0, as is often the case. From
standing wave theory, a cable length less than (.lambda./10) will
replicate the invertor produced high frequency PWM pulse without over
voltage at the motor terminals.
TABLE I
______________________________________
Effect of Invertor Semiconductors
on AC Motor Voltage Surge
Voltage Surge
At Motor
Semiconductor Rise Twice V.sub.DC
V.sub.DC Bus
Device Type Time at (4) at (10)
______________________________________
Gate Turnoff Thyristor (GTO)
1 ms 774 ft 309 ft
Bipolar Junction Transistor
0.3 ms 386 ft 155 ft
(BJT) 0.07 ms 54 ft 29 ft
Insulated Gate Bipolar
Transistor (IGBT)
______________________________________
Presently, the widespread use of IGBT technology with its fast rise and
fall switching times produces twice overvoltages at the motor terminals
for drive-motor cable distances exceeding 54 ft. Since this distance is
exceeded in practically 100% of all drive applications, there is now an
urgent need to conceive a simple yet effective apparatus used with AC
motors for eliminating line voltage reflections.
In addition to twice overvoltages, overvoltages greater than twice the DC
bus voltage level are caused by fast IGBT switching frequencies and fast
IGBT dv/dt rise times interacting with two different common switch
modulating techniques referred to as "double pulsing" and "polarity
reversal".
Referring to FIG. 2, double pulsing will be described in the context of an
IGBT inverter generated line-to-line voltage V.sub.i applied to a line
cable and a resulting motor line-to-line terminal voltage V.sub.m.
Initially, at time .tau..sub.1, the line is shown in a fully-charged
condition (V.sub.i (.tau..sub.1)=V.sub.m (.tau..sub.1)=V.sub.DC). A
transient motor voltage disturbance is initiated in FIG. 2 by discharging
the line at the inverter output to zero voltage, starting at time
.tau..sub.2, for approximately 4 .mu.sec. The pulse propagation delay
between the inverter terminals and motor terminals is proportional to
cable length and is approximately 1 .mu.sec for the assumed conditions. At
time .tau..sub.3, 1 .mu.sec after time .tau..sub.2, a negative going
V.sub.DC voltage has propagated to the motor terminals. In this example, a
motor terminal reflection coefficient Kt is nearly unity. Thus, the motor
reflects the incoming negative voltage and forces the terminal voltage
V.sub.m to approximately negative bus voltage:
V.sub.m (.tau..sub.3)=V.sub.m (.tau..sub.1)-V.sub.DC
(1+Kt).apprxeq.-V.sub.DC Eq. 7
A reflected wave (-V.sub.DC) travels from the motor to the inverter in 1
.mu.sec and is immediately reflected back toward the motor. Where an
inverter reflection coefficient Ki is approximately negative unity, a
positive V.sub.DC pulse is reflected back toward the motor at time
.tau..sub.4. Therefore, at time .tau..sub.4 the discharge at time
.tau..sub.2 alone causes a voltage at the motor terminal such that:
V.sub.m (.tau..sub.4)=V.sub.m (.tau..sub.1)-V.sub.DC (1+Kt)-V.sub.DC
KiKt(1+Kt).apprxeq.V.sub.DC Eq. 8
In addition, at time .tau..sub.4, with the motor potential approaching
V.sub.DC due to the .tau..sub.2 discharge, the inverter pulse V.sub.i
(.tau..sub.4) arrives and itself recharges the motor terminal voltage to
V.sub.DC. Pulse V.sub.i (.tau..sub.4) is reflected by the motor and
combines with V.sub.m (.tau..sub.4) to achieve a peak value of
approximately three times the DC rail value:
V.sub.m (.tau..sub.4 +)=V.sub.m (.tau..sub.1)-V.sub.DC (1+K.sub.t)-V.sub.DC
K.sub.i K.sub.t (1+K.sub.t)+V.sub.i
(.tau..sub.4)(1+K.sub.t).apprxeq.3V.sub.DC Eq. 9
Referring to FIG. 3 polarity reversal will be described in the context of
an IGBT inverter generated line-to-line voltage V.sub.il and a resulting
motor line-to-line voltage V.sub.ml. Polarity reversal occurs when the
firing signal of one supply line is transitioning into overmodulation
while the firing signal of another supply line is simultaneously
transitioning out of overmodulation. Overmodulation occurs when a
reference signal magnitude is greater than the maximum carrier signal
magnitude so that the on-time or off-time of a switch is equal to the
duration of the carrier period. Polarity reversal is common in all types
of PWM inverter control.
Initially, the inverter line-to-line voltage V.sub.il (.tau..sub.5) is zero
volts. At time .tau..sub.6, the inverter voltage V.sub.il (.tau..sub.6) is
increased to V.sub.DC and, after a short propagation period, a V.sub.DC
pulse is received and reflected at the motor terminals thus generating a 2
V.sub.DC pulse across associated motor lines. At time .tau..sub.7, the
line-to-line voltage switches polarity (hence the term polarity reversal)
so that the inverter voltage V.sub.il (.tau..sub.7) is equal to -V.sub.DC
when the line-to-line motor voltage V.sub.ml (.tau..sub.7) has not yet
dampened out to a DC value (i.e. may in fact be 2 V.sub.DC ). After a
short propagation period, the -V.sub.DC inverter pulse reaches the motor,
reflects, and combines with the inverter reflected pulse -V.sub.DC and the
positive voltage 2 V.sub.DC on the motor. The combination generates an
approximately -3 V.sub.DC line-to-line motor voltage V.sub.ml
(.tau..sub.8) at time .tau..sub.8.
In reality, the amplitude of overvoltages will often be less than described
above due to a number of system variables including line AC resistance
damping characteristics, DC power supply level, pulse dwell time, carrier
frequency f.sub.c modulation techniques, and less than unity reflection
coefficients (Kt and Ki).
Voltage surges are generally recognized as undesirable for a plurality of
reasons. For example, the supply lines that supply the voltage to a motor
are electrically insulated to withstand a specified level of voltage.
Under normal circumstances where supply line voltage is less than the
specified level, supply line insulation functions properly for much longer
than the life of the motor. However, the useful life of a supply line can
be cut short where the voltage passing through the supply line regularly
exceeds the level of voltage for which the supply line was designed.
Voltage surges caused by reflected waves often present voltage having an
amplitude high enough to damage supply line insulation. Insulation failure
can lead to high voltage short circuit problems which can, in turn, lead
to costly damage of other motor components as well.
In addition to damaging line insulation, a voltage surge can directly
damage a stator winding if the surge penetrates, and is mostly absorbed
by, the initial coils of the stator winding. A stator winding is an
iterative structure having a plurality of series connected winding coils.
When a voltage enters a stator winding, the voltage propagates along the
winding beginning with the first coil. Some of the voltage is absorbed in
the first coil and the rest is propagated onto the latter coils. Ideally,
the voltage is designed to be distributed evenly among the coils under
steady sinewave voltage operation.
In reality, however, because of the reflected voltage waves impressed on
the invertor square wave pulse shape of a voltage surge, voltage
distribution can be unevenly distributed and result in undue and
potentially damaging dielectric stress on certain of the motor windings.
Modern semiconductor switches used in PWM invertors and other types of
invertors produce voltage pulses having relatively fast rise times and
thus having steep front ends. A voltage surge enhances the vertical aspect
of the front end of each pulse and produces an exceedingly steep front
end.
When an exceedingly steep voltage surge of twice DC bus amplitude enters a
stator winding, the voltage difference across the first few coils is
extremely high as the potential difference across adjacent windings
increases rapidly. The turn-to-turn stray capacitance of the first coil is
the first parasitic component to encounter the incoming voltage surge and
takes the brunt of the surge before an attenuated voltage wave propagates
onto the latter coils.
The stator winding insulation, like the line insulation, can be irreparably
damaged by repetitive twice amplitude voltage surges occurring at the
invertor semiconductor switching rate, typically 2 KHZ to 15 KHZ with IGBT
invertors. Insulation burnout is particularly problematic in the case of
stator winding insulation as winding insulation must be minimized to
maintain a compact motor design.
The industry has employed several different hardware solutions to reduce
overvoltages. According to a simple reactor solution, three inductors are
provided, a separate one of the inductors placed in series with each of
the three supply lines between an ASD and three motor terminals.
According to another solution a sinewave filter is linked to the supply
lines wherein this filter includes three capacitors and three inductors. A
separate inductor is positioned in series with each supply line. One
capacitor is linked between each pair of supply lines.
According to yet another solution a dv/dt filter is linked to the three
supply lines between an ASD drive and a motor. The filter includes three
inductors, three resistors and three capacitors. Again, a separate
inductor is positioned in series with each supply line. A separate
resistor is linked in series with a separate capacitor between each pair
of supply lines.
According to one other solution a resistor-inductor-diode (RLD) filter is
linked to the supply lines. The RLD filter includes six diodes, three
inductors and two resistors. A separate inductor is positioned in series
with each supply line. The diodes are arranged in series pairs to form
three parallel diode legs between positive and negative terminals. A node
between the diodes of each leg is linked to a separate supply line and the
positive and negative terminals are connected through separate resistors
to positive and negative DC drive buses, respectively.
While each of the overvoltage solutions identified above effectively reduce
overvoltages, each solution suffers from at least one and typically a
plurality of the following shortcomings. Among other shortcomings, the
solutions above can result in a 3 to 5% voltage drop at the motor
terminals at rated current (e.g. the reactor and dv/dt filter solutions),
are configured using relatively large components and therefore require
large volumes, require a large number of components and therefore are
relatively expensive to configure, provide only poor/slow dynamic response
to a motor load, create periodic instability, cause line-to-line neutral
voltage to be undamped, cause resonant conditions in line-to-neutral
voltage, cause rise times which vary as a function of cable length, and/or
can only be used with specific (e.g. short) cable lengths.
One other solution for dealing with twice overvoltage is described in U.S.
patent application Ser. No. 08/799,737 entitled APPARATUS USED WITH AC
MOTORS FOR ELIMINATING LINE VOLTAGE REFLECTIONS filed by the present
inventor on Feb. 12, 1997 which is assigned to the assignee of the present
case and is incorporated herein by reference. According to that solution,
a terminator network is linked to three motor voltage supply lines to
essentially eliminate overvoltages. The terminator includes at least three
resistors and three capacitors, one resistor and one capacitor arranged in
series between each two supply lines. The terminator overcomes many of the
shortcomings described above with respect to other prior art solutions but
still has some disadvantages. First, the terminator is linked to a control
system at the terminal end of the supply lines. While this is not a
problem in many applications, in many other applications the line sections
adjacent motor terminal might not be accessible or might be located in a
hazardous environment. In addition, the terminator cannot clamp
line-to-neutral voltage on a solid grounded system.
Thus, it would be advantageous to have a relatively compact apparatus for
efficiently and inexpensively eliminating or substantially reducing
voltage surges due to reflected waves which could be located in an
accessible and non-hazardous location.
BRIEF SUMMARY OF THE INVENTION
The inventive apparatus virtually eliminates destructive reflected waves
and also functions to reduce inverter output common mode electromagnetic
interference (EMI) line-to-ground current noise. To this end, the
inventive apparatus includes a plurality of phase inductors and resistors
in combination with a common mode choke (CMC). Specifically, given a
three-line supply configuration, the apparatus includes three inductors
and three resistors. A separate inductor is placed in series with each
supply line and a separate resistor is placed in parallel with each
inductor. Each supply line is linked to the CMC. Importantly, each
inductor-resistor pair is linked between an inverter and an associated
line (i.e., is at the inverter end of the line as opposed to the terminal
end). By selecting inductor-resistor pairs appropriately, peak line
voltage magnitude can be maintained essentially near the maximum output
voltage of the inverter (i.e. near a DC bus voltage V.sub.dc).
In operation, when an inverter generates a pulse, when the pulse reaches an
associated inductor-resistor pair, initially the inductor has a high
impedance so that current is forced through the resistor. The magnitude of
the voltage across the resistor and hence on an attached supply line
during this initial period of high inductor impedance can be controlled by
selecting the resistor value. Preferably, the resistor is chosen such that
the supply line voltage during this initial period rises to approximately
half the maximum inverter output voltage.
Eventually, inductor impedance decreases, current begins to flow through
the inductor and the parallel resistor is effectively removed from the
circuit (i.e., effectively becomes an open circuit). At this time, the
line voltage rises to the level of the inverter output voltage and is
provided to an associated motor terminal. The duration of the initial
period of high inductor impedance is selectable by choosing the inductor
value.
When a pulse is received at the motor terminal, if any portion of the pulse
is reflected as is typical, when the reflected pulse reaches the
inductor-resistor pair, once again the inductor has a high impedance and
the reflected pulse is dissipated by the resistor. Thus, the terminal
reflected pulse or backward traveling pulse cannot be re-reflected thereby
increasing line voltage.
Thus, one object of the invention is to essentially eliminate or minimize
reflected waves on supply lines. The inventive apparatus advantageously
solves both the 2 pu and 3 pu reflected wave voltage problems, for various
combinations of drive carrier frequency and very long cable length by
maintaining near ideal drive bus voltage magnitude for reflected wave
motor voltage so that the safe operating envelope of conventional motor
insulation is not exceeded. By limiting the reflected wave peak voltage
value to the DC bus voltage V.sub.dc, the pulse rise time needs to be only
minimally sloped to be within the safe operating envelope so that minimal
pulse distortion occurs. Another objective is to achieve the
aforementioned object simply and inexpensively. To this end, minimal
components are required and the required components are inexpensive.
One other object is to provide an apparatus which meets the above objects,
yet can advantageously be positioned adjacent an inverter instead of at
the terminal ends of supply lines. While the inventive apparatus can be
used at the terminal end of a supply line, it can also be used at the
inverter end and is thus easy to implement into existing drive/motor
systems.
Another object is to meet the above objects in an efficient manner. To this
end, the inductors are chosen such that the high impedance inductor period
is minimized, thereby ensuring that only minimal energy is dissipated by
the parallel resistors.
The phase resistors and the CMC operate together to reduce the magnitude of
noise in the line-to-ground current without appreciably affecting the
optimum line-to-line waveforms determined by the parallel inductors and
resistors.
Another advantage of the inventive apparatus is that the low impedance of
the apparatus at low fundamental output frequencies also allows AC drive
auto-tune procedures to be done without disconnecting the apparatus. Drive
auto tune encompasses identifying motor stator winding inductance and
resistance values. In addition, the inventive apparatus is designed using
transmission line theory to match inverter output impedance to cable surge
impedance. Cable impedance is approximately constant over the I hp to 500
hp range. Therefore, it is possible to use the components selected in a
single horsepower configuration (e.g. 5 hp) to achieve design goals of
eliminating reflected waves and reducing EMI currents with minimal
performance degradation for all horsepowers within the 1 to 500 horsepower
range.
These and other objects, advantages and aspects of the invention will
become apparent from the following description. In the description,
reference is made to the accompanying drawings which form a part hereof,
and in which there is shown a preferred embodiment of the invention. Such
embodiment does not necessarily represent the full scope of the invention
and reference is made therefor, to the claims herein for interpreting the
scope of the invention.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
FIG. 1 is a schematic diagram of a high frequency equivalent circuit of
both a supply line and a stator winding;
FIG. 2 is a graph illustrating greater than twice over voltage on a motor
due to inverter modulated double pulsing, an inverter line-to-line voltage
generated by PWM modulator firing signals and a resulting uncompensated
line-to-line motor voltage of greater than twice voltage magnitude;
FIG. 3 is a graph illustrating greater than twice over voltage due to
inverter modulated polarity reversal, including an inverter line-to-line
voltage generated by PWM modulator firing signals and a resulting
uncompensated line-to-line motor voltage of greater than twice voltage
magnitude;
FIG. 4 is a schematic diagram of the inventive apparatus linked to supply
lines between an inverter and a motor;
FIG. 5(a) is a graph illustrating exemplary signals used by a PWM inverter
to produce high frequency voltage pulses; FIGS. 5(b) and 5(c) are graphs
illustrating PWM firing signals generated by comparison of the signals of
FIG. 5(a) and FIG. 5(d) is a graph illustrating a high frequency pulse
generated by the firing pulses of FIGS. 5(b) and 5(c);
FIG. 6 is a graph illustrating single phase high frequency voltage pulses
and a resulting associated fundamental low frequency alternating voltage;
FIG. 7 is a graph illustrating line-to-line output voltage between two
supply lines and a resulting fundamental low frequency alternating
voltage;
FIG. 8 is a graph with a detail expansion of the pulse train of FIG. 7
showing pulse rise and fall times;
FIG. 9 is a graph illustrating an inverter generated pulse, a resulting
pulse at a motor terminal without the eliminator and a resulting terminal
pulse with the eliminator;
FIG. 10 is an equivalent circuit schematic representation of a portion of
FIG. 4;
FIG. 11a is a graph illustrating resistor-inductor phase angle vs.
frequency with the resistor fixed at 33 ohms and various inductor values;
FIG. 11b shows resistor-inductor impedance magnitude vs. frequency with
the resistor fixed at 33 ohms and various inductor values; and FIG. 11c is
similar to FIG. 11a, albeit with a fixed inductor of 200 uh and varying
resistor values;
FIG. 12a is a graph illustrating the reflected wave phenomenon where the
inverter is not employed; and FIG. 12b is similar to FIG. 12a, albeit with
an inventive apparatus having too high of a resistor valve;
FIG. 13 is a schematic representing the common mode or line-to-ground EMI
current paths in the cable and motor with the inventive filter network and
a CMC; and
FIG. 14 includes various waveforms corresponding to eliminator currents
with and without a common mode choke, the first three waveforms measured
without a choke and the last four measured with a choke.
DETAILED DESCRIPTION OF THE INVENTION
In the description which follows, like reference characters, numbers and
symbols will be used to represent identical or similar elements throughout
the several views. In addition, while the invention is described below in
the context of a three phase motor control system, because each of the
three phases operates in essentially the same manner, unless there is some
important synergy between the hardware or operation of two phases, only
one of the three phases and signals related thereto will be explained in
detail.
A. Hardware
The present invention will be described in the context of the exemplary PWM
inverter 9 shown in FIG. 4. Inverter 9 is shown connected to a PWM
controller 20, a DC voltage source 18, a reflected wave eliminator 6
according to the present invention, a set of transmission lines or cables
43, 44 and 45 (collectively referred to by the numeral 7) and a motor 19.
Source 18 provides a high voltage rail 48 and a low voltage rail 49. For
the purposes of this explanation source 18 may be represented by a series
combination including a positive DC source 22 and a negative DC source 21
separated by a reference node 0. A capacitor 89 is provided across source
18 to essentially filter the DC voltage to obtain a ripple free DC voltage
between rails 48 and 49. Typical values of capacitor 89 range between
1,000 uf and 20,000 uf dependent on drive horsepower rating.
Motor 19 includes three stator windings 35, 36 and 37 connected in a
Y-configuration as well known in the art, each winding 35, 36 and 37
linked to a separate transmission line 44, 43, 45, respectively at unique
motor terminals 30, 31, 32, respectively. Distal ends of lines 43, 44 and
45 are linked to intermediate nodes 95, 96 and 97, respectively. Each line
43, 44 and 45 is characterized by a line inductance L and a line
capacitance C exists between each pair of transmission lines 43-44, 43-45
and 44-45 (see also FIG. 1 in this regard).
Inverter 9 consists of six solid state switches 12-17 (BJT, GTO, IGBT or
other transistor technology devices may be used) arranged in series pairs
12-13, 14-15 and 16-17 between positive and negative DC rails 48, 49,
repsectively. Each switch 12-17 is coupled with an inverse parallel
connected diode 23-29, repsectively.
Each pair of switches 12-13, 14-15, and 16-17, makes up a separate leg 39,
40 or 41 of inverter 9 and has a common node 91, 92 or 93, respectively,
which is electrically linked to one of terminals 31, 30 and 32 (and thus
to a unique stator winding 35, 36 or 37), repsectively, after passing
through respective phases of eliminator 6 and transmission lines 43, 44 or
45. For example, node 91 is linked through a first phase of eliminator 6
to intermediate node 95 which is in turn directly linked via transmission
line 43 to terminal 31.
Each switch 12-17 is also electrically connected by a firing line 51-56 to
controller 20. Controller 20 provides turn on and turn off signals to each
of switches 12-17 to turn the switches on and off thereby alternately
connecting motor terminals 30, 31 and 32 to positive and negative DC rails
48, 49, respectively.
Eliminator 6 is linked in series between inverter nodes 91, 92 and 93 and
intermediate nodes 95, 96 and 97 (i.e. between inverter 9 and transmission
lines 43, 44 and 45). Eliminator 6 consists of a common mode choke (CMC),
three relatively short sections of transmission line 29, 34 and 38, and a
filter network 8. Filter 8 includes three inductors 102, 104 and 106 and
three resistors 101, 103 and 105. As well known in the controls art, while
inverter output currents through nodes 91, 92 and 93 should all vary with
time and all three currents will never be identical at the same time, the
combined values of the inverter output currents should equal zero amps.
When the combined currents do not add to a zero value, a common mode
current is said to exist which adversely affects motor control. CMC 107 is
provided to eliminate common mode currents.
To this end, as well known in the art, CMC 107 includes a flux guiding core
(not illustrated) around which transmission lines 29, 34 and 38 are
wrapped so that common mode currents through the lines (i.e. currents
which do not add to a zero value) are effectively canceled. Each line 29,
34 and 38 is linked to an inverter output node 91, 92, or 93,
respectively, is wrapped around the core in the same direction an
identical number of times and is terminated at an intermediate node 83,
85, 86, respectively. In operation, current through the lines induces a
flux in the core. Because intended currents generated by inverter 9 add to
a zero value, only common mode currents induce flux in the core. The flux
provides a high impedance to common mode currents and thereby effectively
eliminates the common mode currents.
Inductors 102, 104 and 106 are chosen so as to have essentially identical
electrical operating characteristics. Similarly, resistors 101, 103 and
105 are chosen to have essentially identical electrical operating
characteristics. Inductor 102 is linked between intermediate nodes 83 and
95, inductor 104 is linked between nodes 85 and 96 and inductor 106 is
linked between intermediate nodes 86 and 97. Resistors 101, 103 and 105
are linked in parallel with inductors 102, 104 and 106. Preferably,
eliminator 6 is mounted in close physical proximity to inverter 9 (i.e.
transmission lines 29, 34 and 38 are relatively short compared to lines
43, 44 and 45).
Inductors 102, 104 and 106 and resistors 101, 103 and 105 are specifically
chosen based on transmission line theory to eliminate undesirable voltage
waves on lines 43, 44 and 45. The factors considered when choosing
inductor and resistor values and how to chose the values correctly are
explained in more detail below.
B. Operation
Initially, operation of inverter 9 to generate voltage waveforms at
inverter output nodes 91, 92 and 93 is explained and then operation of
eliminator 107 to eliminate reflected and standing waves is explained.
1. Inverter Operation
To simplify this explanation, unless there is some synergy between legs 39,
40 and 41 only operation of leg 39 will be explained here in detail. With
respect to operation of leg 39, referring again to FIG. 4, controller 20
operates to turn switches 12 and 13 on and off in a repetitive sequence
that alternately connects the high and low voltage rails 48, 49 to, and
produces a series of high frequency voltage pulses at, terminal 31.
Referring also to FIG. 5a, signals 67 and 68 used by controller 20 to
generate firing pulses to turn switches 12 and 13 on and off are
illustrated. A carrier signal 67 is perfectly periodic and operates at
what is known as a carrier frequency fc. Carrier frequencies fc used in
PWM drives typically range between I KHz to 10 KHz. A modulating signal 68
has a much greater period than the carrier frequency 67. A modulating
signal frequency fm corresponds to the desired fundamental output
frequency of waveforms to be generated by inverter 9.
Referring also | | |
