A power amplifier, particularly a gradient amplifier of a magnetic resonance tomography apparatus, has at least one switched output stage containing a power bridge circuit formed by a number of switch elements and connected to a floating intermediate circuit voltage, as well as at least one digital pulse width modulator that generates pulse-width-modulated control signals for all switch elements from a digital input signal in order to generate at least one output stage voltage according to an output stage switch clock. The digital pulse width modulator is preceded by a pre-modulator for forming the digital input signals, with at least one of the digital input signals containing an offset, preferably corresponding to half an LBS.

A power amplifier, particularly a gradient amplifier of a nuclear magnetic resonance tomography apparatus, has at least one switched output stage containing a power bridge circuit formed by a number of switch elements, the bridge circuit being connected to a floating intermediate circuit voltage, as well as at least one digital pulse width modulator that generates pulse-width-modulated control signals for all switch elements of the power bridge circuit from digital input signals in order to generate at least one output stage voltage according to an output stage switching clock. The digital pulse width modulator has a modulator base element that contains a counter with an output for a counter reading, at least one comparator with an input for receiving the counter reading, a further input for receiving one of the digital input signals, an output binary signal representing a "smaller-than" comparison, and a further output for a further binary signal representing a "greater-than" comparison of the counter reading to the digital input signal. Circuitry follows the comparator for generating the control signals from the binary signals.

An integrated circuit such as a host adapter for connection to a system bus of a host computer includes a memory interface for a local memory including a serial memory such as an SEEPROM. The memory interface is capable of unsupervised multi-bit transfers between the serial memory and a data register in the memory interface. The host computer to access the serial memory starts the memory interface on a multi-bit access (i.e., read, write, or erase), checks a busy bit in the memory interface to determine when the access is complete, and accesses the data register. Thus, the host computer is decoupled from bit-by-bit management of transfers, and the integrated circuit or a bus device incorporating the integrated circuit requires less software overhead for use of serial memory. The memory interface further includes protection circuitry that prevents writing or erasing of a portion of the memory that a flag designates as protected. The flag is in a register that does not permit changes unless the host adapter is in a state such as corresponding to a target abort exists. Accordingly, the host can write or erase protected memory by causing a target abort, changing the flag to unprotect the memory, and then changing the memory. Since the state is unlikely to exist when a software might unintentionally access the flag, unintended changes to the protected memory are unlikely.

A method of automated distributed resource monitoring in a large distributed computing environment, wherein a given master resource comprises a set of given computing resources. The method begins by associating a set of one or more "cells" with a set of given computing resources that comprise the master resource. Each cell preferably is associated with a respective one of the set of given computing resources and has a set of one or more attributes whose values collectively define a "state" of the cell. Whenever a change in an attribute of a given cell effects a change in that cell's state, the attribute change is propagated across each cell directly impacted by the cell state change, as well as to those observing cells that may be indirectly affected.

A power supply circuit for an ion engine suitable for a spacecraft is coupled to a bus having a bus input and a bus return. The power supply circuit has a first primary winding of a first transformer. An upper inverter circuit is coupled to the bus input and the first primary winding. The power supply circuit further includes a first lower inverter circuit coupled to the bus return and the first primary winding. The second primary winding of a second transformer is coupled to the upper inverter circuit. A second lower inverter circuit is coupled to the bus return and the second primary winding.