A state machine design which can be used to realize extremely short flag generation delays. The present invention also realizes the benefit of having an extremely high MTBF. The present invention generates a set of next state variables that are generated from a combination of three previous state variables and three additional inputs representing a logical "OR" of a read half-full and write half-full flag WRH, an external write clock input, and an external read clock input. The next state variables are derived from a product of the previous state variables, a complement signal of the previous state variables, and the signal WRH. The half-full flag is generated using digital logic decoding techniques that manipulate inputs from the three next state variables, a read clock signal and a write clock signal.
A state machine comprising a first input receiving a first write clock, a second input receiving a first read clock, a third input receiving a first programmable Almost Empty look-ahead signal, a fourth input receiving a second write clock, a fifth input receiving a second read clock, and a sixth input receiving a second programmable Almost Empty look-ahead signal is disclosed. The state machine manipulates the inputs to produce an output signal representing an Almost Empty output flag that is at a first logic state when a FIFO is Almost Empty and is at a second logic state when the FIFO is Not Almost Empty.
An apparatus and method for controlling an asynchronous dual port FIFO memory is provided. The asynchronous FIFO may operate at frequencies satisfying 0.5f.sub.2 <f.sub.1 <f.sub.2 or 0.5f.sub.1 <f.sub.2 <f.sub.1, where f.sub.2 is the write frequency if f.sub.1 is the read frequency, or vice versa. A FIFO in accordance with the present invention comprises a dual port random access memory, a read pointer, a write pointer, a synchronization circuit and a status indicator. In the FIFO design, the read pointer indicating the read address is a simple sequential counter, and the write pointer indicating the write address is a Gray code counter. Gray code to sequential count converters are used to convert the Gray codes to sequential counts. The synchronization circuit synchronizes the write pointer and the read pointer using a read clock. A status indicator with simple circuits is provided to indicate if the FIFO is almost full or empty.
The present invention concerns a circuit comprising a memory, a flag/array address circuit and a flag logic circuit. The memory may be configured to read and write data in response to one or more memory address signals. The flag/array address circuit may be configured to present one or more flag address signals in response to (i) one or more enable signals and (ii) a control signal. The flag logic circuit may be configured to present one or more logic flags in response to the one or more flag address signals.
