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Description  |
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AUTHORIZATION
A portion of the disclosure of this patent document contains material which
is subject to copyright protection. The copyright owner has no objection
to the facsimile reproduction by anyone of the patent documents or the
patent disclosure, as it appears in the Patent or Trademark Office patent
file or records, but otherwise reserves all copyright rights whatsoever.
FIELD OF THE INVENTION
The present invention relates to the field of signal processing and in
particular to filtering of received signals to generate a delayed value of
the received signal.
BACKGROUND OF THE INVENTION
In signal processing it is sometimes necessary to utilize a value of a
received input signal as it existed at a prior time in order to perform a
desired control or information processing function. Digital systems
generally sample incoming signals at a very high rate which is on the
order of many times a second. In known systems which perform control or
information processing functions based on received signals, a large amount
of storage is required in digital systems and a large number of delay
elements are required in analog systems if the value of the incoming
signal as it existed in the past is needed. For example, an electronic
automatic temperature controller (EATC) used on an automotive vehicle
utilizes a temperature sensor to generate a signal indicative of ambient
temperature for use by the EATC. Unless the sensor is placed in a position
far removed from the engine compartment, heat generated by the engine,
exhaust or other components is likely to affect the temperature detected
by the sensor. When the sensor is located in the engine compartment at a
position to be exposed to air entering the engine compartment, it has been
found to provide an accurate reading when the vehicle is in motion.
However, when the vehicle is standing the temperature sensor gives a much
higher reading than normal because of the increased air temperature in the
engine compartment. In such a circumstance, it is helpful to have the
value of temperature as it existed several minutes in the past, such as
before the vehicle stopped, so that the EATC can accurately determine the
existing ambient temperature. With certain finite impulse response
filters, if a five minute delay is desired for a signal sampled every
second, a system utilizing a finite impulse response filter of known type
would need 300 storage or delay elements. One solution is for the EATC to
utilize a vehicle velocity signal which is indicative of vehicle velocity
in order to determine when the signal from the temperature sensor should
be ignored. However, if the vehicle velocity signal is not already being
used by the EATC, then use of such a signal adds to the cost and physical
complexity of the EATC. In addition, even if the vehicle velocity signal
is available to the EATC, an accurate value of ambient air temperature is
still required. If the vehicle is stopped momentarily, then a temperature
value indicative of the temperature before the vehicle stopped, will still
be required.
Accordingly, there is a need for a filter which generates a delayed value
of an input signal without requiring the large number of storage or delay
elements required by known systems.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to generate a delayed value
of a value of a received input signal without utilizing a large number of
storage or delay elements.
In accordance with the primary object, in one aspect of the invention an
input signal is delayed a predetermined amount of time with a first order
infinite impulse response (IIR) filter which comprises a summing element
which generates an intermediate value as a function of an input value, a
first value and a second value. A first multiplier generates an output
value as a function of the intermediate value and a first weighting value.
The IIR filter also comprises a residual generation element responsive to
the summing element for generating a numerical residual value indicative
of a difference in resolution between the output value and the
intermediate value. A first delay element, which is responsive to the
residual generation element delays the numerical residual value by a
predetermined amount of time to generate the first value. A second delay
element, which is responsive to the first multiplier, delays the output
value by the predetermined amount of time to generate a delayed output
value, and a second multiplier, which is responsive to the second delay
element, generates the second value as a function of the delayed output
value and a second weighting value.
In another aspect of the invention, a plurality of filters utilizing the
principles of the aforementioned IIR filter are cascaded to generate a
substantial time delay.
An advantage of at least certain embodiments is that a delay on the order
of several minutes may be generated without utilizing a large number of
storage or delay elements.
These and other features and advantages of the present invention may be
better understood by considering the following detailed description of
preferred embodiments of the invention. In the course of this description,
reference will be made to the attached drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of a first embodiment of a filter stage which
embodies the invention.
FIG. 2 is a schematic diagram of a plurality of cascaded filter stages.
FIG. 3 is a schematic diagram of an alternative embodiment of a filter
stage which embodies the invention.
FIG. 4(a) is a graph showing the response of a preferred embodiment to an
input signal.
FIG. 5 is a schematic diagram of an electronic automatic temperature
controller utilizing the principles of the present invention.
DETAILED DESCRIPTION
FIG. 1 shows a block diagram of a single filter stage which is operable on
a digital computer which utilizes floating point arithmetic. The filter
stage is a first order infinite impulse response (IIR) filter with an
input port 2 and an output port 4. The first order IIR has a sample time
represented by a variable h, which in a preferred embodiment has a value
of one second. Multiplier 6 multiplies an input signal by a weighting
factor h/.tau., where .tau. represents a time constant in seconds. The
output from multiplier 6 is coupled to an input of a summing element 8
which provides an output value of the filter stage through output port 4.
Storage element 10 has its input coupled to output port 4 and operates to
provide a delayed version of the value existing at output 4, to multiplier
12. Multiplier 12 multiplies the output of storage element 10 by a
weighting factor (1-h/.tau.), and provides the output to summing element
8.
Multipliers 6 and 12, summer 8, and delay element 10 are preferably
implemented by a programmable digital computer. Alternatively, the filter
stage may be implemented by specialized digital or analog circuits.
A preferred embodiment advantageously creates an N.sup.th order infinite
impulse response digital filter by cascading in series N stages identical
to the stage of FIG. 1. The result is filter 220 of FIG. 2, where the
input port to the first stage 221 of filter 220 is coupled to the output
port of source 201 and the output port of the last stage 223 of filter 220
is coupled to utilization circuit 240. The input port of any other stage,
besides the first and last in FIG. 2, such as stage 222, is coupled to the
output port of a preceding stage. The resulting z-transform equation H(z)
of filter 220, ignoring any numerical round-off errors, is given by the
following relationship:
##EQU1##
where z.sup.-1 is a unit time delay, .tau. represents the time constant of
each of the filter stages and N represents the number of filter stages.
Each of the filter stages 221, 222 and 223 of FIG. 2 advantageously
provides a time delay, with the cascaded delay of all of the filter stages
of FIG. 2 generating a substantial time delay without utilizing a large
number of delay elements. In FIG. 2 source 201 provides an output in the
form of a sequence of digitized signal values. In an alternative
embodiment, source 201 may provide an analog continuous-time signal. In
such an embodiment if filter 220 is a digital filter, a sample-and-hold
circuit and an analog-to-digital converter are required to condition the
source signal into a sequence of sampled signal values.
FIG. 3 shows an alternate embodiment, which is preferred for fixed point,
or integer, arithmetic. This stage receives an input signal through input
port 32 and provides an output through output port 34. Summing element 40
receives input signal 33 from input port 32, and provides an output 41
which is the sum of the value of input signal 33, and signals 37 and 48.
Multiplier 44 multiplies signal 41 with a weighting factor 1/.tau. to
generate output signal 45. As used in the fixed point filter shown in FIG.
3, .tau. is a time constant in terms of the sample period. Storage element
46 receives output signal 45 and generates signal 47 which is a delayed
version of output signal 45. Multiplier 36 multiplies signal 47 with a
weighting factor .tau.-1 to generate signal 37. The operations performed
by elements 42 and 39 advantageously perform a resolution enhancement
function which improves the accuracy of the filter stage. Masking element
42 masks signal 41 with a mask value .tau.-1 to generate signal 43 which
is delayed by storage element 39 to generate signal 41. As will be
appreciated by those skilled in the art in view of the present disclosure,
the masking element generates a numerical residual value which is
indicative of the difference in resolution between the value at 34 and the
value at 41. Values 41, 43 and 48 are preferably generated using
double-precision storage locations to provide enhanced resolution. The
residual generation function is preferably performed by a masking element
such as seen in FIG. 3. In an alternative embodiment, the residual
generation function is performed by a modulo operation using a modulo
value of .tau., where .tau.=2.sup.m, is an integer which represents a
value selected to achieve a desired delay with a desired number of filter
stages.
The filter stage seen in FIG. 3 is preferably implemented with a digital
computer executing a stored program. As will be appreciated by those
skilled in the art in view of the present disclosure, the filter stage of
FIG. 3 may be implemented with digital circuitry which comprise either
discrete components or are integrated onto a single integrated circuit. As
will be appreciated by those skilled in the art in view of the present
disclosure, multipliers 36 and 44 involve simple bit shifts and
subtraction and can be implemented with relatively few program steps or
logic elements and shift registers. Summing element 40 and delay elements
39 and 46 may also be implemented with logic elements and shift registers.
An N.sup.th order filter for fixed point, or integer, arithmetic is
synthesized by cascading in series N stages identical to the stage of FIG.
3 to generate a series of delay stages as seen in FIG. 2 and described
above.
FIG. 4 of the drawings shows an input 401 to filter 220 with a
corresponding output at 402 of filter 220. Each of the stages of filter
220 may be of the type shown in FIG. 1 or FIG. 3. In FIG. 4, ten filter
stages are used with the value .tau. for each filter having a value of 32.
For the floating point filter in FIG. 4, h preferably has a value of one
second. As can be seen in FIG. 4, the cascaded stages of filter 220 delay
and smooth the output of source 201. It is understood that line 402
represents an output of a cascaded filter utilizing filters of the type
shown either in FIG. 1 or FIG. 3. The delay time can be significant and is
approximately given by the product N.tau.h, where h is the sampling rate.
The approximation improves as N increases. In order to provide a delay of
N.tau.h time shifts, filter 220 advantageously requires only N delay or
storage elements, whereas a finite impulse response filter would require
[N.tau.] delay or storage elements.
FIG. 5 of the drawings shows an Electronic Automatic Temperature Controller
(EATC) installed in a vehicle which utilizes the principles of the present
invention. In FIG. 5, EATC 500 receives a temperature signal from
temperature sensor 535. Temperature sensor 535 is of known type and is
positioned in the engine compartment to be directly exposed to air as it
enters the engine compartment while the vehicle is in motion. EATC 500
responds to signals from temperature sensor 535 and from user inputs
entered at 560 to generate control signals for changing the temperature
and volume of air entering the interior compartment of the vehicle. In a
preferred embodiment, the interior compartment is a passenger compartment.
In alternative embodiments, the interior compartment may be a storage
compartment which may be a refrigerated compartment or other type of
compartment kept within a predefined temperature range. As can be seen in
FIG. 5, control signals from EATC 500 control the operation of a plurality
of temperature alteration systems which take the form of ventilation 510,
heating 520 and air conditioning 530 units of the vehicle.
EATC 500 preferably comprises a microcomputer including a central processor
unit (CPU) 541, input and output (I/O) port 540, read only memory (ROM)
542 for storing control programs, random access memory (RAM) 543, for
temporary data storage which may also be used for counters or timers, and
a conventional data bus. EATC 500 operates under stored program control to
receive input signals, and to generate output signals to perform the above
described control functions.
As previously indicated, in a preferred embodiment, the present invention
is advantageously implemented by means of a microprocessor and memory
containing suitable programs and data structures for providing the desired
control functions. The following C language program listing illustrates to
those skilled in the art, an implementation of a preferred embodiment.
______________________________________
/*
************************************************************
********
Five-minute ago filter: critically damped IIR filter --
*
* Copyright (c) 1993 Ford Motor Company
*
*
************************************************************
********
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define E 2.718281828
/* Function prototypes: */
/* float camel (double, double, double, int, int, int) ; */
/* float icamel (int, int, int, int, int, int); */
/* globals: */
float camel (sys.sub.-- in, tint, tau, order, init.sub.-- flag, details)
double sys.sub.-- in, tint, tau;
int order, init.sub.-- flag, details;
{ /* tint: sample time interval, tau: time constant, (n-th) order filter
*/
/* -- This is a series-cascaded (order times) single pole filter. */
int i,j;
static int first.sub.-- time = 1;
static int noa.sub.-- wts, nob.sub.-- wts;
static float * casc.sub.-- in, * a.sub.-- wts, * casc.sub.-- out, *
b.sub.-- wts;
static float s.sub.-- out;
static float alpha, beta;
/* Initialization: */
if (first.sub.-- time) {
if (details > 1) fprintf (stderr,"-- starting up camel
--.backslash.n");
alpha = tint / tau;
beta = 1.0 - alpha;
/* Forward weights: */
noa.sub.-- wts = order + 1 ; /* no. of cascade sections */
if (details > 3) fprintf (stderr,"-- allocating casc.sub.-- in &
a.sub.-- wts --.backslash.n");
casc.sub.-- in = (float *) calloc (noa.sub.-- wts, sizeof(float));
a.sub.-- wts = (float *) calloc (noa.sub.-- wts, sizeof(float));
if (details > 3) fprintf (stderr,"-- order = %d --.backslash.n",
order);
if (details > 3) fprintf (stderr," a.sub.-- wts @%p .backslash.n",
a.sub.-- wts);
for (i=0; i < noa.sub.-- wts ; i++) {
casc.sub.-- in[i] = 0.0;
/* coupling between sections: */
for unity pulse response */ gamman;
a.sub.-- wts[i] = alpha; for unity step response */
if (details > 3)
fprintf (stderr," a.sub.-- wts[%d] = %7.3f.backslash.n", i, a.sub.--
wts[i]);
}
/* Recurrent weights: */
if (details > 3) fprintf (stderr,"-- allocating casc.sub.-- out &
b.sub.-- wts --.backslash.n");
nob.sub.-- wts = order + 1; /* addl. for offset (not used) */
casc.sub.-- out = (float *) calloc (nob.sub.-- wts, sizeof(float));
b.sub.-- wts = (float *) calloc (nob.sub.-- wts, sizeof(float));
b.sub.-- wts[0] = 0.0; /* - not used - */
casc.sub.-- out[0] = 0.0;
for (j=1; j < nob.sub.-- wts; j++) {
casc.sub.-- out[j] = 0.0;
b.sub.-- wts[j] = beta;
}
first.sub.-- time = 0;
if (details > 1) {
fprintf(stderr,"--- %dth order weights initialized: ---.backslash.n",
order);
fprintf(stderr," a.sub.-- wts @%p.backslash.n", a.sub.-- wts);
fprintf(stderr," b.sub.-- wts @%p.backslash.n", b.sub.-- wts);
for(i=0;i < noa.sub.-- wts;i++) {
fprintf(stderr," a.sub.-- wts[%d] = %7.4f.backslash.n", i, a.sub.--
wts[i]);
}
for (j=0; j < nob.sub.-- wts; j++) {
fprintf(stderr," b.sub.-- wts[%d] = %7.4f.backslash.n", j, b.sub.--
wts[j]);
}
}
}
if (init.sub.-- flag) {
if (details > 0) fprintf (stderr,"-- (re-)initializing ccamel
--.backslash.n");
for (i=0; i < noa.sub.-- wts; i++) {
casc.sub.-- in[i] = 0.0;
}
for (j=0; j < nob.sub.-- wts; j++) {
casc.sub.-- out[j] = 0.0;
}
}
/* Starts here: (above is mostly overhead) ************** */
crasc.sub.-- in[0] = sys.sub.-- in;
for (i=1; i < noa.sub.-- wts; i++) {
casc.sub.-- in[i] = b.sub.-- wts[i]*casc.sub.-- out[i] + a.sub.--
wts[i-1]*casc.sub.-- in[i-1];
casc.sub.-- out[i] = casc.sub.-- in[i];
}
s.sub.-- out = casc.sub.-- out[order];
if(details > 4) {
fprintf(stdefr,"-- Input Cascade:");
for(i=0; i < noa.sub.-- wts;i++) {
fprintf(stderr,"%8.4f", casc.sub.-- in[i]);
}
fprintf(stderr,".backslash.n");
}
if(details > 4) {
fprintf(stderr,"-- Output Cascade:");
for(j=0; j < nob.sub.-- wts;j++) {
fprintf(stderr,"%8.4f", casc.sub.-- out[j]);
}
fprintf(stderr,".backslash.n");
}
return(s.sub.-- out);
}
int icamel (sys.sub.-- in, tau, order, accumulate, init.sub.-- flag;
details)
int sys.sub.-- in, tau, order, accumulate, init.sub.-- flag, details;
{ /* tint: not used, tau: time constant in steps, (n-th) order filter */
/* -- This is a series-cascaded (order times) single pole filter. */
int i,j;
static int first.sub.-- time = 1;
static int noa.sub.-- wts, nob.sub.-- wts;
static int * casc.sub.-- in, *a.sub.-- wts, * casc.sub.-- out, * b.sub.--
wts, * accum ;
static int s.sub.-- out;
static int alpha, beta;
/* Initialization: */
if(first.sub.-- time) {
if (details > 1) fprintf(stderr,"-- starting up icamel
--.backslash.n");
alpha = 1;
beta = tau - 1;
/* Forward weights: */
noa.sub.-- wts = order + 1; /* no. of cascade sections */
if (details > 3) fprintf(stderr,"-- allocating casc.sub.-- in &
a.sub.-- wts --.backslash.n");
casc.sub.-- in = (int *) calloc(noa.sub.-- wts, sizeof(int));
a.sub.-- wts = (int *) calloc(noa.sub.-- wts, sizeof(int));
if(details > 3) {
fprintf(stderr,"-- order = %d --.backslash.n", order);
fprintf(stderr,"a.sub.-- wts @%p:.backslash.n", a.sub.-- wts);
}
for (i=0; i < noa.sub.-- wts; i++) {
casc.sub.-- in[i] = 0;
/* coupling between sections: */
a.sub.-- wts[i] = alpha; /* for unity step response */
}
/*Recurrent weights: */
if (details > 3) fprintf(stderr,"-- allocating casc.sub.-- out &
b.sub.-- wts --.backslash.n");
nob.sub.-- wts = order + 1; /* addl. for offset (not used) */
casc.sub.-- out = (int *) calloc(nob.sub.-- wts, sizeof(int));
accum = (int *) calloc(nob.sub.-- wts, sizeof(int));
b.sub.-- wts = (int *) calloc (nob.sub.-- wts, sizeof(int));
b.sub.-- wts[0] = 0; /* - not used - */
casc.sub.-- out[0] = 0;
for (j=1;j < nob.sub.-- wts;j++) {
casc.sub.-- out[j] = 0;
accum[j] = 0;
b.sub.-- wts[j] = beta;
}
first.sub.-- time = 0;
if (details > 1) {
fprintf(stderr,"--- %dth order weights initialized: ---.backslash.n",
order);
fprintf(stderr," a.sub.-- wts @%p :.backslash.n", a.sub.-- wts);
for (i=0; i < noa.sub.-- wts; i++) {
fprintf(stderr," a.sub.-- wts[%d] = %4d.backslash.n", i, a.sub.--
wts[i]);
}
fprintf(stderr," b.sub.-- wts @%p :.backslash.n", b.sub.-- wts);
for (j=0; j < nob.sub.-- wts; j++) {
fprintf(stderr," b.sub.-- wts[%d] = %4d.backslash.n", j, b.sub.--
wts[j]);
}
}
if (init.sub.-- flag) {
if (details > 0) fprintf(stderr,"-- (re-)initializing icamel
--.backslash.n");
for (i=0; i < noa.sub.-- wts; i++) {
casc.sub.-- in[i] = 0;
}
for (j=0;j < nob.sub.-- wts;j++) {
casc.sub.-- out[j] = 0;
}
}
/* Starts here: (above is mostly overhead) ************** */
casc.sub.-- n[0] = sys.sub.-- in;
for (i=1; i < noa.sub.-- wts; i++) {
accum[i] += b.sub.-- wts[i]*casc.sub.-- out[i] + a.sub.-- wts[i-1]*casc.s
ub.-- in[i-1];
casc.sub.-- out[i] = accum[i]/tau;
if (accumulate) accum[i] = accum[i] % tau;
else accum[i] = 0;
casc.sub.-- in[i] = casc.sub.-- out[i];
}
s.sub.-- out = casc.sub.-- out[order];
if(details > 4) {
fprintf(stderr,"-- Input Cascade:");
for(i=0; i < noa.sub.-- wts; i++) {
fprintf(stderr,"%4d", casc.sub.-- in[i]);
}
fprintf(stderr,".backslash.n");
fprintf(stderr,"-- Accumulator:");
for (j=0; j < nob.sub.-- wts; j++) {
fprintf(stderr,"%4d", accum[j]);
}
fprintf(stderr,".backslash.n");
fprintf(stderr,"-- Output Cascade:");
for (j=0;j < nob.sub.-- wts;j++) {
fprintf(stderr,"%4d", casc.sub.-- out[j]);
}
fprintf(stderr,".backslash.n");
}
return (s.sub.-- out);
}
______________________________________
As can be seen by those skilled in the art, the above program implements a
method for generating an output value which is delayed for a predetermined
length of time from a received time varying input signal by first
generating an input value corresponding to the received input signal.
Second, the input value is multiplied with a first weighting value to
generate a first intermediate value. Third, the first intermediate value
is added to a third intermediate value to generate an intermediate output
value. Fourth, the input value is replaced with the intermediate output
value to generate an input value for a subsequent delay stage. Fifth, the
intermediate output value is stored to a storage location, for use in the
subsequent delay stage. Sixth, the third intermediate value is generated
by retrieving the stored intermediate output value from the storage
location and multiplying the intermediate output value with a second
weighting value. In a preferred embodiment, the storage location
containing the intermediate output value is initialized with a
predetermined value. Seventh, a different storage location for storage of
a subsequent intermediate output value is selected. This different storage
location will be used as the storage location by the subsequent delay
stage to store the intermediate output value. Eighth, the output value is
generated by periodically repeating steps two through seven a
predetermined number of times, to execute a predetermined number of delay
stages. As can be seen from the above description, such an embodiment
utilizes a limited number of storage locations while generating an output
value which is delayed a substantial amount of time from the input value.
It is to be understood that the specific mechanisms and techniques which
have been described are merely illustrative of one application of the
principles of the invention. Numerous modifications may be made to the
methods and apparatus described without departing from the true spirit and
scope of the invention.
* * * * *
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