Method and apparatus for coupling signals between two circuits operating in different clock domains

Claims

I claim:

1. An apparatus for applying a second signal to a second device operating in a second clock domain defined by a second clock signal responsive to a first signal received from a first device operating in a first clock domain defined by a first clock signal, the apparatus comprising:

a first logic circuit coupled to receive the first signal and the first clock signal, the first logic circuit generating an intermediate signal responsive to each transition of the first clock signal subsequent to the first signal being received unless a reset signal is being applied to the first logic circuit, the first logic circuit comprising:

a third logic circuit to receive the first signal and the reset signal, the third logic circuit generating an output signal responsive to the first signal unless the reset signal is being applied to the third logic circuit;

a clocking circuit generating enable pulses responsive to respective transitions of the first clock signal, the clocking circuit generating enable pulses responsive to both positive and negative transitions of the first clock signal; and

a fourth logic circuit coupled to receive the output signal of the third logic circuit and the enable pulses from the first clocking circuit, the fourth logic circuit generating the intermediate signal responsive to receiving the output signal from the third logic circuit and one of the enable pulses, the fourth logic circuit comprising first and second gating circuit receiving the output signal of the third logic circuit, the first gating circuit generating the intermediate signal responsive to receiving the output signal from the third logic circuit and an enable pulse generated responsive to a positive transition of the first clock signal, the second logic gate generating the intermediate signal responsive to receiving the output signal from the third logic circuit and an enable pulse generated responsive to a negative transition of the first clock signal; and

a second logic circuit coupled to the first logic circuit to receive the intermediate signal and the second clock signal, the second logic circuit generating the second signal responsive to a transition of the second clock signal subsequent to the intermediate signal being generated, the second logic circuit generating the reset signal responsive to the second signal.

2. The coupling circuit of claim 1 wherein the fourth logic circuit further comprises a latch circuit continuously generating the intermediate signal responsive to receiving the output signal from the third logic circuit and one of the enable pulses until the second logic circuit generates the reset signal.

3. An apparatus for applying a second signal to a second device operating in a second clock domain defined by a second clock signal responsive to a first signal received from a first device operating in a first clock domain defined by a first clock signal, the apparatus comprising:

a first logic circuit coupled to receive the first signal and the first clock signal, the first logic circuit generating an intermediate signal responsive to each transition of the first clock signal subsequent to the first signal being received unless a reset signal is being applied to the first logic circuit; and

a second logic circuit coupled to the first logic circuit to receive the intermediate signal and the second clock signal, the second logic circuit generating the second signal responsive to a transition of the second clock signal subsequent to the intermediate signal being generated, the second logic circuit generating the reset signal responsive to the second signal, the second logic circuit comprising:

a clocking circuit generating enable pulses responsive to respective transitions of the second clock signal, the clocking circuit generating enable pulses responsive to both positive and negative transitions of the first clock signal, and

a third logic circuit coupled to receive the intermediate signal from the first logic circuit and the enable pulses from the clocking circuit, the third logic circuit generating the second signal responsive to receiving the intermediate signal from the first logic circuit and one of the enable pulses, the third logic circuit comprising first and second gating circuit receiving the intermediate signal from the first logic circuit, the first gating circuit generating the second signal responsive to receiving the intermediate signal from the first logic circuit and an enable pulse generated responsive to a positive transition of the second clock signal, the second logic gate generating the second signal responsive to receiving the intermediate signal from the first logic circuit and an enable pulse generated responsive to a negative transition of the second clock signal.

4. A coupling circuit for coupling a first signal from a first device operating in one clock domain defined by a first clock signal to a second device operating in a second clock domain defined by a second clock signal, the coupling circuit comprising:

a first clocking circuit generating first enable pulses responsive to respective transitions of the first clock signal, the first clocking circuit generating first enable pulses responsive to both positive and negative transitions of the first clock signal;

a second clocking circuit generating second enable pulses responsive to respective transitions of the second clock signal;

a first gating circuit including a latch circuit generating an intermediate signal until the latch circuit is reset, the latch circuit being reset responsive to an output signal, the first gating circuit generating the intermediate signal responsive to receiving the first signal from the first device and a first enable pulse from the first clocking circuit, the first gating circuit comprising first and second logic gates receiving the first signal, the first logic gate generating the intermediate signal responsive to receiving the first signal and a first enable pulse generated responsive to a positive transition of the first clock signal, the second logic gate generating the intermediate signal responsive to receiving the first signal and a first enable pulse generated responsive to a negative transition of the first clock signal; and

a second gating circuit applying the output signal to the second device responsive to receiving the intermediate signal from the first gating circuit and a second enable pulse from the second clocking circuit.

5. A coupling circuit for coupling a first signal from a first device operating in one clock domain defined by a first clock signal to a second device operating in a second clock domain defined by a second clock signal, the coupling circuit comprising:

a first clocking circuit generating first enable pulses responsive to respective transitions of the first clock signal;

a second clocking circuit generating second enable pulses responsive to respective transitions of the second clock signal, the second clocking circuit generating second enable pulses responsive to both positive and negative transitions of the second clock signal;

a first gating circuit generating an intermediate signal responsive to receiving the first signal from the first device and a first enable pulse from the first clocking circuit; and

a second gating circuit applying the output signal to the second device responsive to receiving the intermediate signal from the first gating circuit and a second enable pulse from the second clocking circuit, the second gating circuit comprising third and fourth logic gates receiving the intermediate signal from the first and second logic gates, respectively, the third logic gate generating the output signal responsive to receiving the intermediate signal from the first logic gate and a second enable pulse generated responsive to a positive transition of the second clock signal, the second logic gate generating the output signal responsive to receiving the intermediate signal from the second logic circuit and a second enable pulse generated responsive to a negative transition of the second clock signal.

6. A coupling circuit for coupling a first signal from a first device operating in one clock domain defined by a first clock signal to a second device operating in a second clock domain defined by a second clock signal, the coupling circuit comprising:

a first clocking circuit generating first enable pulses responsive to respective transitions of the first clock signal;

a second clocking circuit generating second enable pulses responsive to respective transitions of the second clock signal, the second clocking circuit generating second enable pulses responsive to both positive and negative transitions of the second clock signal;

a first gating circuit generating an intermediate signal responsive to receiving the first signal from the first device and a first enable pulse from the first clocking circuit; and

a second gating circuit applying the output signal to the second device responsive to receiving the intermediate signal from the first gating circuit and a second enable pulse from the second clocking circuit, the second gating circuit comprising first and second logic gates receiving the intermediate signal, the first logic gate generating the output signal responsive to receiving the intermediate signal and a second enable pulse generated responsive to a positive transition of the second clock signal, the second logic gate generating the output signal responsive to receiving the intermediate signal and a second enable pulse generated responsive to a negative transition of the second clock signal.

7. A coupling circuit for coupling a first signal from a first device operating in one clock domain defined by a first clock signal to a second device operating in a second clock domain defined by a second clock signal, the coupling circuit comprising:

a logic gate having a signal input terminal, an output terminal, and a control terminal, the signal input terminal being coupled to the first device to receive the first signal, the logic gate coupling the input terminal to the output terminal until a disable input is applied to the control terminal;

a first clocking circuit having a clock input terminal, and an input terminal coupled to the output terminal of the logic gate, the first clocking circuit coupling the input terminal to an output terminal responsive to one transition of the first clock signal;

a first latch circuit having a trigger input coupled to the output terminal of the first clocking circuit, the first latch circuit generating a latched signal at an output terminal responsive to the trigger signal until the latch circuit is reset by a reset signal;

a second clocking circuit having a clock input terminal, and an input terminal coupled to the output terminal of the logic gate, the second clocking circuit coupling the input terminal to an output terminal responsive to another transition of the first clock signal;

a second latch circuit having a trigger input coupled to the output terminal of the second clocking circuit, the second latch circuit generating a latched signal at an output terminal responsive to the trigger signal until the latch circuit is reset by the reset signal;

a third clocking circuit having a clock input terminal, and an input terminal coupled to the output terminal of the first latch circuit, the third clocking circuit coupling the input terminal to an output terminal responsive to one transition of the second clock signal;

a fourth clocking circuit having a clock input terminal, and an input terminal coupled to the output terminal of the second latch circuit, the fourth clocking circuit coupling the input terminal to an output terminal responsive to another transition of the second clock signal;

a combining circuit having first and second input terminals coupled to the output terminals of the third and fourth clocking circuits, respectively, the combining circuit generating an output signal at an output terminal responsive to receiving a latched signal clocked from a respective latch by either said third or said fourth clock circuit, the output signal being coupled to the second device, the output terminal of the combining circuit being coupled to the disable terminal of the logic gate and to the reset terminals of the latch circuits to disable the logic gate and reset the latch circuits responsive to the output signal from the combining circuit.

8. The coupling circuit of claim 7 further comprising:

a signal routing circuit altering the coupling between the respective output terminals of the first and second latch circuits to the input terminals of the third and fourth clocking circuits, the signal routing circuit coupling the output terminal of the first latch circuit to the input terminal of the fourth clock circuit and the output terminal of the second latch circuit to the input terminal of the third clock circuit responsive to a signal routing control signal applied to a control terminal of the signal routing circuit; and

a control circuit coupled to the signal routing circuit, the control circuit applying the signal routing control signal to the control input terminal of the signal routing circuit.

9. The coupling circuit of claim 8 wherein the control circuit comprises a phase comparison circuit receiving the first and second clock signals at first and second input terminals, the control circuit generating the signal routing control circuit as a function of the phase relationship between the first and second clock signals.

10. The coupling circuit of claim 7 wherein the signal routing circuit comprises:

a first pair of inverters having respective inputs coupled to the output terminals of the first and second latch circuits and respective output terminals coupled to respective input terminals of the third and fourth clocking circuits, the first pair of inverters being enable responsive to a first logic level of the signal routing control signal; and

a second pair of inverters having respective inputs coupled to the output terminals of the first and second latch circuits and respective output terminals coupled to respective input terminals of the fourth and third clocking circuits, the second pair of inverters being enable responsive to a second logic level of the signal routing control signal.

11. The coupling circuit of claim 10 wherein the control circuit comprises a phase comparison circuit receiving the first and second clock signals at first and second input terminals, the control circuit generating a signal routing control signal having the first logic level responsive to one timing relationship between the first and second clock circuits and a signal routing control signal having the second logic level responsive to another timing relationship between the first and second clock circuits.

12. A memory device, comprising:

a control circuit adapted to receive a command from an external source and generate control signals responsive thereto, the control circuit including a clock generator circuit adapted to receive an external clock signal and to generate an internal clock signal, a read transfer initiate signal, a write transfer initiate signal, a read data initiate signal, and a write data initiate signal, the timing of the read clock signal and the write clock signal being controlled by an external device;

a memory array coupled to the control circuit, the memory array having a plurality of memory cells adapted to store write data and output read data;

an addressing circuit coupled to the memory array and the control circuit, the addressing circuit adapted to receive addresses from an external source and select a memory cell in the memory array corresponding thereto;

a read data path having a read register coupled to the control circuit, the read register being adapted to couple read data from the memory array to an externally accessible terminal responsive to the read clock signal subsequent to the read data start signal being applied to a control input terminal;

a write data path having a write register coupled to the control circuit, the write register being adapted to couple write data from the externally accessible terminal to the memory array responsive to a write register clock signal subsequent to a write data start signal being applied to a control input terminal;

respective first and second coupling circuits having an input terminal connected to the control circuit to receive a respective transfer initiate signal and an output terminal connected to the control input terminal of a respective register, each of the coupling circuits comprising:

a first clocking circuit generating first enable pulses responsive to respective transitions of a first clock signal synchronized to the internal clock signal;

a second clocking circuit generating second enable pulses responsive to respective transitions of a second clock signal, the timing of the second clocking being controlled by the external device;

a first gating circuit generating an intermediate signal responsive to receiving the respective transfer initiate signal from the control circuit and a first enable pulse from the first clocking circuit; and

a second gating circuit applying the respective data start signal to the respective register responsive to receiving the intermediate signal from the first gating circuit and a second enable pulse from the second clocking circuit.

13. The memory device of claim 12 wherein the second clocking circuit generates second enable pulses responsive to both positive and negative transitions of the second clock signal, and wherein the second gating circuit comprises third and fourth logic gates receiving the intermediate signal from the first and second logic gates, respectively, the third logic gate generating the respective data start signal responsive to receiving the intermediate signal from the first logic gate and a second enable pulse generated responsive to a positive transition of the second clock signal, the second logic gate generating the respective data start signal responsive to receiving the intermediate signal from the second logic circuit and a second enable pulse generated responsive to a negative transition of the second clock signal.

14. The memory device of claim 12 wherein the second clocking circuit generates second enable pulses responsive to both positive and negative transitions of the second clock signal, and wherein the second gating circuit comprises first and second logic gates receiving the intermediate signal, the first logic gate generating the respective data start signal responsive to receiving the intermediate signal and a second enable pulse generated responsive to a positive transition of the second clock signal, the second logic gate generating the respective data start signal responsive to receiving the intermediate signal and a second enable pulse generated responsive to a negative transition of the second clock signal.

15. The memory device of claim 12 wherein the first gating circuit comprises a latch circuit generating the intermediate signal until the latch circuit is reset, the latch circuit being reset responsive to the respective data start signal.

16. The memory device of claim 15 wherein the first clocking circuit generates first enable pulses responsive to both positive and negative transitions of the first clock signal, and wherein the first gating circuit comprises first and second logic gates receiving the first signal, the first logic gate generating the intermediate signal responsive to receiving the respective transfer initiate signal and a first enable pulse generated responsive to a positive transition of the first clock signal, the second logic gate generating the intermediate signal responsive to receiving the respective transfer initiate signal and a first enable pulse generated responsive to a negative transition of the first clock signal.

17. The memory device of claim 12 wherein the memory device comprises a dynamic random access memory device.

18. The memory device of claim 17 wherein the dynamic random access memory device comprises a packetized dynamic random access memory device.

19. A memory device, comprising:

a control circuit adapted to receive a command from an external source and generate control signals responsive thereto, the control circuit including a clock generator circuit adapted to receive an external clock signal and to generate an internal clock signal, a read transfer initiate signal, a write transfer initiate signal, a read data initiate signal, and a write data initiate signal, the timing of the read clock signal and the write clock signal being controlled by an external device;

a memory array coupled to the control circuit, the memory array having a plurality of memory cells adapted to store write data and output read data;

an addressing circuit coupled to the memory array and the control circuit, the addressing circuit adapted to receive addresses from an external source and select a memory cell in the memory array corresponding thereto;

a read data path having a read register coupled to the control circuit, the read register being adapted to couple read data from the memory array to an externally accessible terminal responsive to the read clock signal subsequent to the read data start signal being applied to a control input terminal;

a write data path having a write register coupled to the control circuit, the write register being adapted to couple write data from the externally accessible terminal to the memory array responsive to a write register clock signal subsequent to a write data start signal being applied to a control input terminal;

a first coupling circuit having an input terminal connected to the control circuit to receive the read transfer initiate signal and an output terminal connected to the control input terminal of the read register, the first coupling circuit comprising:

a first logic circuit coupled to receive the read transfer initiate signal and a first clock signal in the same clock domain as the internal clock signal, the first logic circuit generating a first intermediate signal responsive to each transition of the first clock signal subsequent to the read transfer signal being received unless a first reset signal is being applied to the first logic circuit; and

a second logic circuit coupled to the first logic circuit to receive the first intermediate signal and a second clock signal in the same domain as the read clock signal, the second logic circuit generating the read data start signal responsive to a transition of the second clock signal subsequent to the first intermediate signal being generated, the second logic circuit generating the first reset signal responsive to the read data start signal; and

a second coupling circuit having an input terminal connected to the control circuit to receive the write transfer initiate signal and an output terminal connected to the control input terminal of the write register, the second coupling circuit comprising:

a third logic circuit coupled to receive the write transfer initiate signal and a third clock signal in the same clock domain as the internal clock signal, the third logic circuit generating a second intermediate signal responsive to each transition of the third clock signal subsequent to the write transfer signal being received unless a second reset signal is being applied to the third logic circuit; and

a fourth logic circuit coupled to the third logic circuit to receive the second intermediate signal and a fourth clock signal in the same domain as the write clock signal, the fourth logic circuit generating the write data start signal responsive to a transition of the fourth clock signal subsequent to the second intermediate signal being generated, the fourth logic circuit generating the second reset signal responsive to the write data start signal.

20. The memory device of claim 19 wherein the first and third clock signals are identical to each other, and the second and fourth clock signals are identical to each other.

21. The memory device of claim 19 wherein the second and fourth logic circuits each comprises:

a clocking circuit generating enable pulses responsive to respective transitions of the respective second and fourth clock signals; and

a logic gate coupled to receive the respective intermediate signal from the respective first or third logic circuit and the enable pulses from the clocking circuit, the logic gate generating the respective data start signal responsive to receiving the respective intermediate signal from the respective first or third logic circuit and one of the enable pulses.

22. The memory device of claim 19 wherein the first and third logic circuits each comprises:

a first logic gate receiving a respective transfer initiate signal and a respective reset signal, the first logic gate generating an output signal responsive to the respective transfer initiate signal unless a respective reset signal is being applied to the first logic gate;

a clocking circuit generating enable pulses responsive to respective transitions of the respective first or third clock signal; and

a second logic gate coupled to receive the output signal of the first logic gate and the enable pulses from the clocking circuit, the second logic gate generating the respective intermediate signal responsive to receiving the output signal from the first logic gate and one of the enable pulses.

23. The memory device of claim 22 wherein the clocking circuit generates enable pulses responsive to both positive and negative transitions of the respective first or third clock signal, and wherein the second logic gate comprises first and second gating circuits receiving the output signal of the first logic gate, the first gating circuit generating the respective intermediate signal responsive to receiving the output signal from the first logic gate and an enable pulse generated responsive to a positive transition of the respective first or third clock signal, the second gating circuit generating the respective first or third intermediate signal responsive to receiving the output signal from the first logic gate and an enable pulse generated responsive to a negative transition of the respective first or third clock signal.

24. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;

a memory controller coupled to the processor through the processor bus; and

a memory device coupled to the processor through the processor bus, comprising:

a control circuit adapted to receive a command from the memory controller and generate control signals responsive thereto, the control circuit including a clock generator circuit adapted to receive an external clock signal and to generate an internal clock signal, a read transfer initiate signal, a write transfer initiate signal, a read data initiate signal, and a write data initiate signal, the timing of the read clock signal and the write clock signal being controlled by the memory controller;

a memory array coupled to the control circuit, the memory array having a plurality of memory cells adapted to store write data and output read data;

an addressing circuit coupled to the memory array and the control circuit, the addressing circuit adapted to receive addresses from the memory controller and select a memory cell in the memory array corresponding thereto;

a read data path having a read register coupled to the control circuit, the read register being adapted to couple read data from the memory array to an externally accessible responsive to the read clock signal subsequent to the read data start signal being applied to a control input terminal;

a write data path having a write register coupled to the control circuit, the write register being adapted to couple write data from the externally accessible terminal to the memory array responsive to a write register clock signal subsequent to a write data start signal being applied to a control input terminal;

a first coupling circuit having an input terminal connected to the control circuit to receive the read transfer initiate signal and an output terminal connected to the control input terminal of the read resister, the first coupling circuit comprising:

first logic circuit coupled to receive the read transfer initiate signal and a first clock signal in the same clock domain as the internal clock signal, the first logic circuit generating a first intermediate signal responsive to each transition of the first clock signal subsequent to the read transfer signal being received unless a first reset signal is being applied to the first logic circuit; and

a second logic circuit coupled to the first logic circuit to receive the first intermediate signal and a second clock signal in the same domain as the read clock signal, the second logic circuit generating the read data start signal responsive to a transition of the second clock signal subsequent to the first intermediate signal being generated, the second logic circuit generating the first reset signal responsive to the read data start signal; and

a second coupling circuit having an input terminal connected to the control circuit to receive the write transfer initiate signal and an output terminal connected to the control input terminal of the write register, the second coupling circuit comprising:

a third logic circuit coupled to receive the write transfer initiate signal and a third clock signal in the same clock domain as the internal clock signal, the third logic circuit generating a second intermediate signal responsive to each transition of the third clock signal subsequent to the write transfer signal being received unless a second reset signal is being applied to the third logic circuit; and

a fourth logic circuit coupled to the third logic circuit to receive the second intermediate signal and a fourth clock signal in the same domain as the write clock signal, the fourth logic circuit generating the write data start signal responsive to a transition of the fourth clock signal subsequent to the second intermediate signal being generated, the fourth logic circuit generating the second reset signal responsive to the write data start signal.

25. The memory device of claim 24 wherein the first and third clock signals are identical to each other, and the second and fourth clock signals are identical to each other.

26. The memory device of claim 24 wherein the second and fourth logic circuits each comprises:

a clocking circuit generating enable pulses responsive to respective transitions of the respective second and fourth clock signals; and

a logic gate coupled to receive the respective intermediate signal from the respective first or third logic circuit and the enable pulses from the clocking circuit, the logic gate generating the respective data start signal responsive to receiving the respective intermediate signal from the respective first or third logic circuit and one of the enable pulses.

27. The memory device of claim 24 wherein the first and third logic circuits each comprises:

a first logic gate receiving a respective transfer initiate signal and a respective reset signal, the first logic gate generating an output signal responsive to the respective transfer initiate signal unless a respective reset signal is being applied to the first logic gate;

a clocking circuit generating enable pulses responsive to respective transitions of the respective first or third clock signal; and

a second logic gate coupled to receive the output signal of the first logic gate and the enable pulses from the clocking circuit, the second logic gate generating the respective intermediate signal responsive to receiving the output signal from the first logic gate and one of the enable pulses.

28. The memory device of claim 27 wherein the clocking circuit generates enable pulses responsive to both positive and negative transitions of the respective first or third clock signal, and wherein the second logic gate comprises first and second gating circuits receiving the output signal of the first logic gate, the first gating circuit generating the respective intermediate signal responsive to receiving the output signal from the first logic gate and an enable pulse generated responsive to a positive transition of the respective first or third clock signal, the second gating circuit generating the respective first or third intermediate signal responsive to receiving the output signal from the first logic gate and an enable pulse generated responsive to a negative transition of the respective first or third clock signal.

TECHNICAL FIELD

This invention relates to coupling signals from one electronic device to another, and more particularly to coupling signals between electronic devices having different clock domains defined by respective clocks that may differ from each other.

BACKGROUND OF THE INVENTION

Many electronic devices operate in a synchronous manner in which the timing of signals in the device are controlled by a clock signal. The transitions of the clock signal occur at substantially the same time throughout the circuit, thereby ensuring that signals coupled or created responsive to the transitions of the clock signal are properly synchronized to each other.

Although synchronism between signals can be maintained when the same clock signal, or clock signals derived from the same clock signal, are used throughout a circuit. It is substantially more difficult to properly synchronize signals coupled from one electronic device to another when the electronic devices operate in different clock domains defined by different clock signals.

With reference to FIG. 1, a first electronic device 10 receives a signal S.sub.i and a clock signal CLKA. The electronic device outputs a signal S.sub.2 responsive to the input signal S.sub.i and transitions of the clock signal CLKA. The signal S.sub.2 is coupled to the input of a second electronic device 12 through a line 14. The second electronic device 12 also receives a second clock signal CLKB. The second clock signal CLKB may have a phase that is different from the phase of the first clock signal CLKA, and it may even have a frequency that is different from the frequency of the first clock signal CLKA. The problem encountered when coupling the signal S.sub.2 from the output of the first device 10 to the input of the second device 12 is illustrated in FIG. 2.

The clock signal CLKA for the first electronic device 10 is shown in FIG. 2A, and the input signal S.sub.i is shown in FIG. 2B as going high at time t.sub.0. By way of example, the first electronic device 10 simply performs a logical AND function of the input signal S.sub.i and the clock signal CLKA to generate the signal S.sub.2. The signal S.sub.2 is shown in FIG. 2C with exponentially rising and falling edges because of the capacitive loading on the line 14 coupling the first electronic device 10 to the second electronic device 12.

An example of a clock signal CLKB.sub.1 having a first phase is illustrated in FIG. 2D. As shown by comparing FIG. 2A with FIG. 2D, the clock signal CLKA for the first electronic device 10 lags the clock signal CLKB.sub.1 for the second electronic device 12. By way of example, it is assumed that the second electronic device 14 simply functions to clock the signal S.sub.2 (FIG. 2C) on either the rising edge of the clock signal CLKB.sub.1 (FIG. 2F) or the falling edge of the clock signal CLKB.sub.1 (FIG. 2G). As shown in FIG. 2F, the second electronic device 12 is incapable of detecting the signal S.sub.2 when the device 12 is clocked on the rising edge of CLKB.sub.1 because the signal S.sub.2 is not present at the input to the electronic device 12 on the rising edge of CLKB.sub.1. However, as shown in FIG. 2G, the second electronic device 14 is able to detect the signal S.sub.2 if the electronic device 12 clocks the signal S.sub.2 on the falling edge of the clock signal CLKB.sub.1. Thus, the second electronic device 12 can function with the first electronic device 10 despite having different clock domains, but only as long as the clock signal CLKB.sub.1 leads the clock signal CLKA. If the electronic device 12 clocks the signal S.sub.2 on the falling edge of CLKB.sub.1, it will not be able to detect the signal S.sub.2 if the clock signal CLKB lags the clock signal CLKA.

An example of a clock signal CLKB.sub.2 that lags the clock signal CLKA is illustrated in FIG. 2E. The first clock signal CLKA is considered to lag the second clock signal CLKB if any transition of the first clock signal CLKA occurs more than 0 degrees and less than 180 degrees after the corresponding transition of the second clock signal CLKB. The first clock signal CLKA is considered to leasd the second clock signal CLKB if any transition of the first clock signal CLKA occurs more than 180 degrees and less than 0 degrees after the corresponding transition of the second clock signal CLKB. Again, it is first assumed that the second electronic device 12 functions to clock the signal S.sub.2 on the rising edge of the clock signal CLKB.sub.2 (FIG. 2H) or the falling edge of the clock signal CLKB.sub.2 (FIG. 2I). As shown in FIG. 2H, the second electronic device 12 is able to detect the signal S.sub.2 if the electronic device 12 clocks the signal S.sub.2 on the rising edge of the clock signal CLKB.sub.2. However, as shown in FIG. 2I, the second electronic device 12 is incapable of detecting the signal S.sub.2 if the electronic device 12 clocks the signal on the falling edge of the clock signal CLKB.sub.2 because the signal S.sub.2 is not present at the input to the electronic device 12 on the falling edge of the clock signal CLKB.sub.2.

It will be apparent from the above discussion that the second electronic device 12 is able to detect the signal S.sub.2 generated by the first electronic device 10 as long as either the second clock signal CLKB leads the first clock signal CLKA and the second electronic device 12 clocks the signal S.sub.2 on the falling edge of CLKB, or the second clock signal CLKB lags the first clock signal and the second electronic device 12 clocks the signal S.sub.2 on the rising edge of CLKB. However, because the first and second electronic devices 10, 12, respectively, are operating in different clock domains, the phase relationship between CLKA and CLKB can change. Therefore, if the choice is made to make the second electronic device 12 clock the signal S.sub.2 on the falling edge of CLKB, it is possible for the clock signal CLKB to lag the first clock signal CLKA. As explained above, the second electronic device 12 will be unable to detect the signal S.sub.2 under these conditions. Similarly, if the choice is made for the second electronic device 12 to clock the signal S.sub.2 on the rising edge of CLKB, it is possible for the clock signal CLKB to lead the first clock signal CLKA. Again, the second electronic device 12 will be unable to detect the signal S.sub.2.

A more concrete example of the problem illustrated FIGS. 1 and 2 is exemplified by a memory device 20 shown in FIG. 3. The memory device 20 illustrated in FIG. 3 is a packetized dynamic random access memory ("DRAM") having an architecture known as SyncLink. However, the problem may also exist to varying degrees with other types of memory devices, such as synchronous DRAMs. The packetized memory device 20 is shown in somewhat generalized form because the specific structure of the memory device 20 is somewhat peripheral to the inventions described herein. However, packetized memory devices 20 are explained in greater detail in the U.S. patent applications Ser. No. 08/877,191 and 08/874,690.626 to Troy A. Manning which are incorporated herein by reference.

The memory device 20 includes a controller 22 that receives a command packet CA, generally containing several multi-bit packet words, a flag signal F indicating the start are a command packet, and a command clock CMDCLK synchronized to the packet words. The command packet CA includes both memory commands, such as read, write, etc., and bank, row and column address information, as well as other information used to initialize or operate the memory device 20.

The memory device 20 also includes a clock generator 24 that receives the command clock CMDCLK as well as control signals from the controller 22. The clock generator 24 produces several clock signals from the command clock CMDCLK, including an internal clock signal ICLK and a read clock signal RCLK. The phase of the internal clock signal ICLK and the phase of the read clock signal RCLK are determined by control signals from the controller 22. The controller 22 uses the internal clock signal ICLK to generate an initiate signal INIT to start the transfer of read data out to the memory device 20 and write data into the memory device 20. The controller 22 also generates a write phase command signal WPHASE that is used in a manner to be explained below.

Address portions of the command packet CA are coupled to address circuitry 28. The address circuitry 28 then applies bank and row addresses to bank/row circuitry 30 and column addresses to column circuitry 32. The structure and operation of this circuitry 30, 32 is well known to one skilled in the art. Basically, the bank/row circuitry 30 selects a memory array 36 or a portion of a memory array 36, and a row of memory cells in that array. The column circuitry 32 selects a column of memory cells in the array, and data is written to or read from the memory cell in the selected row than intersects the selected column.

Data are coupled between an externally accessible data bus terminal DQ and the column circuitry 32 through a data path 40 that includes a read data path 40a and a write data path 40b. The read data path 40a includes a read register 42 and an output buffer 46 that couple read data from the array 36 via the column circuitry 32 to the data bus terminal DQ. The write data path 40b includes an input buffer 50 and a write register 52 that couple write data from the data bus terminal DQ to the array 36 via the column circuitry 32. During a read operation, read data are applied to a data input of the read register 42 and clocked through the read register 42 by the read clock signal RCLK after the initiate signal INIT from the controller 22 has transitioned active high. During a write operation, write data are applied to the write register 52 and clocked through the write register 52 by a clock signal from a phase shift circuit 56 after the initiate signal INIT has transitioned active high. The phase shift circuit 56 generates the clock signal from a data clock signal DCLK applied to the memory device 20 from an external device, such as a memory controller (not shown). The phase of the clock signal applied to the write register 52 relative to the phase of the data clock DCLK is controlled by the phase command signal WPHASE from the controller 22.

In operation, an external device, such as a memory controller, provides a command packet CA to the memory device 20 to set the timing of the read clock RCLK relative to the command clock CMDCLK. Thus, the phase of the read clock RCLK is controlled by the external device. In a similar manner, the phase of the data clock signal DCLK is determined by the external device, such as a memory controller, generating the data clock signal DCLK. In this manner, the external device controls the timing of the memory device 20 applying read data to the external device.

The memory device 20 shown in FIG. 3, when coupled to external devices, such as memory controllers, must operate in two clock domains. The first clock domain is defined by the internal clock signal ICLK, which corresponds to the timing of the control signals from the controller 22. Thus, the functions carried out by the controller 22, such as receiving data from and outputting data to the array 36, and initiating data transfers responsive to the initiate signals INIT, are in the first clock domain. The coupling of data through the read register 42 is in a second clock domain because the coupling of signals through the read register 42 is controlled by the read clock signal RCLK, and the phase of the read clock RCLK is determined by the external device. Similarly, the coupling of signals through the write register 52 is in