A via structure includes a barrier layer disposed between a via plug and an insulating layer surrounding a via hole to impede diffusion of conductive material from the via plug into the insulating layer. The barrier layer is deposited to cover the via side wall after the via hole is formed. The via hole is then filled with a via plug comprised of a conductive material such as copper that is amenable for fine line metallization with submicron and nanometer dimensions. The diffusion rate of copper through the barrier layer is significantly slower than the diffusion rate of copper through the insulating layer surrounding the via hole. With such an impedance of copper diffusion into the insulating layer, the insulating integrity of the insulating layer is preserved.
There is provided a connection structure in which concentration of current in a connection portion of wirings, or of an element and a wiring is prevented. Three slits are formed in each of a first wiring and a second wiring, which extends in a direction perpendicular to a direction in which the first wiring extends, so that distances from the side of a cross internal angle gradually become longer. A portion of a current path is changed by these slits so as to limit current which can flow through the cross internal angle.
A method for forming intermetal dielectric of semiconductor device comprising the steps of: forming a first insulating layer on a semiconductor substrate having device such as transistors therein; forming metal wirings in which a Ti/TiN layer, an Al layer and a TiN layer are stacked successively on the first insulating layer; forming a spacer of TiN layer at side of the metal wirings; forming a second insulating layer on the metal wirings having the spacer and on the first insulating layer, wherein the second insulating layer is made of an insulating material whose deposition rate varies in accordance with the kinds of bottom layers; forming a third insulating layer on the second insulating layer; and polishing the third insulating layer by a chemical mechanical polishing process.
A method for reducing copper diffusion into an inorganic dielectric layer adjacent to a copper structure by doping the inorganic dielectric layer with a reducing agent (e.g. phosphorous, sulfur, or both) during plasma enhanced chemical vapor deposition. The resulting doped inorganic dielectric layer can reduce copper diffusion without a barrier layer reducing fabrication cost and cycle time, as well as reducing RC delay.
A semiconductor device comprises: a lower interconnect formed over a semiconductor substrate; an insulating film formed on the lower interconnect; a via hole penetrating the insulating film to reach the lower interconnect; a first barrier film covering bottom and side surfaces of the via hole; and a metal film filling the via hole covered with the first barrier film. A portion of the first barrier film covering a lower end of the side surface of the via hole is thicker than a portion covering the bottom surface of the via hole.
