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Claims  |
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I claim:
1. A burst address counter comprising:
first to fourth decoder circuits for decoding address signals;
first to fourth multiplexer circuits having first to third input terminals to receive the decoded address signals output from said first to fourth decoder circuits at the first input terminals, respectively, and selectively output one of input
signals input to the first to third input terminals on the basis of a control signal;
first to fourth register circuits for storing output signals representing a burst address and output from said first to fourth multiplexer circuits, respectively;
a first interconnection used in linear and interleave modes of single data rate scheme and connected to input the output signal stored in said first register circuit to the second input terminal of said fourth multiplexer circuit and the output
signals stored in said second to fourth register circuits to the second input terminals of said first to third multiplexer circuits, respectively; and
a second interconnection used in the interleave mode of single data rate scheme and connected to input the output signals stored in said first to third register circuits to the third input terminals of said second to fourth multiplexer circuits,
respectively, and the output signal stored in said fourth register circuit to the third input terminal of said first multiplexer circuit.
2. A counter according to claim 1,
wherein when a burst address in the linear mode of single data rate scheme is to be generated, each of said first to fourth multiplexer circuits is controlled to select the input signal to the first input terminal at the start of the burst
address generation operation and then select the input signal to the second input terminal, and when a burst address in the interleave mode of single data rate scheme is to be generated, each of said first to fourth multiplexer circuits is controlled to
select the input signal to the first input terminal at the start of the burst address generation operation and then select one of the input signal to the second input terminal and the input signal to the third input terminal in accordance with a logic
level of a lower bit of a start address.
3. A counter according to claim 1,
wherein the output signals are stored in said first to fourth register circuits on the basis of a clock signal.
4. A semiconductor memory device including the burst address counter according to claim 1, comprising:
a memory cell array in which a plurality of memory cells are arrayed in a matrix;
a plurality of data buses through which data to be read/written from/in the memory cells propagate;
a read/write control circuit for controlling a data read/write from/in memory cells in said memory cell array, which correspond to two consecutive addresses, and parallelly processing the data between said read/write control circuit and said
plurality of data buses;
a memory cell selection circuit for selecting the memory cells in said memory cell array in accordance with the address signal containing the output signals representing a burst address output from said burst address counter;
a column transfer gate group controlled by said memory cell selection circuit to select a column in said memory cell array;
a first data line for outputting data read out from a plurality of memory cells selected when a predetermined column address signal bit of the address signal is at "0" through said column transfer gate group;
a second data line for outputting data read out from a plurality of memory cells selected when the predetermined column address signal bit is at "1" through said column transfer gate group;
a first sense amplifier for amplifying the data read out from the memory cells and a first data write circuit for writing data in the memory cells, said first sense amplifier and said first data write circuit being connected to said first data
line and having an active period controlled by a column address signal bit other than the predetermined column address signal bit;
a second sense amplifier for amplifying the data read out from the memory cells and a second data write circuit for writing data in the memory cells, said second sense amplifier and said second data write circuit being connected to said second
data line and having an active period controlled by the column address signal bit other than the predetermined column address signal bit;
a first data bus commonly connected to a plurality of sets of first sense amplifiers and first data write circuits having different active periods; and
a second data bus commonly connected to a plurality of sets of second sense amplifiers and second data write circuits having different active periods.
5. A semiconductor memory device according to claim 4,
wherein the memory cell comprises a static memory cell.
6. A semiconductor memory device comprising:
a memory cell array;
a burst address counter for generating a burst address signal as part of a column address signal for designating a column address of said memory cell array on the basis of external address signals; and
a circuit for selecting a memory cell in said memory cell array on the basis of the address signals and the burst address signal output from said burst address counter,
wherein said burst address counter comprises:
first to fourth decoder circuits for decoding the address signals;
first to fourth multiplexer circuits having first to third input terminals to receive the decoded address signals output from said first to fourth decoder circuits at the first input terminals, respectively, and selectively output one of input
signals input to the first to third input terminals on the basis of a control signal;
first to fourth register circuits for storing output signals representing a burst address and output from said first to fourth multiplexer circuits, respectively;
a first interconnection used in linear and interleave modes of single data rate scheme and connected to input the output signal stored in said first register circuit to the second input terminal of said fourth multiplexer circuit and the output
signals stored in said second to fourth register circuits to the second input terminals of said first to third multiplexer circuits, respectively; and
a second interconnection used in the interleave mode of single data rate scheme and connected to input the output signals stored in said first to third register circuits to the third input terminals of said second to fourth multiplexer circuits,
respectively, and the output signal stored in said fourth register circuit to the third input terminal of said first multiplexer circuit.
7. A burst address counter comprising:
first multiplexer circuits each having first and second input terminals to receive an address signal at the second input terminal, select one of input signals input to the first and second input terminals, and output a first output signal
representing a burst address;
first register circuits for storing the first output signals output from said first multiplexer circuits, respectively;
first inverters for inverting the first output signals stored in said first register circuits and inputting the inverted output signals to the first input terminals of said first multiplexer circuits as input signals, respectively;
second multiplexer circuits each having first to third input terminals to receive a decoded address signal at the second input terminal, receive the address signal at the third input terminal, select one of input signals input to the first to
third input terminals, and output a second output signal representing the burst address;
second register circuits for storing the second output signals output from said second multiplexer circuits, respectively; and
second inverters for inverting the second output signals stored in said second register circuits and inputting the inverted output signals to the first input terminals of said second multiplexer circuits as input signals, respectively.
8. A counter according to claim 7,
wherein storage of the first output signal by said first register circuit and storage of the second output signal by said second register circuit are performed on the basis of a clock signal.
9. A counter according to claim 7,
wherein when a burst address in a linear mode of double data rate scheme is to be generated, said first and second multiplexer circuits are controlled to select the input signals to the second input terminals of said first and second multiplexer
circuits at the start of the burst address generation operation and then select the input signals to the first input terminals, and
when a burst address in an interleave mode of double data rate scheme is to be generated, said first and second multiplexer circuits are controlled to select the input signals to the second input terminals of said first multiplexer circuits and
input signals to the third input terminals of said second multiplexer circuits at the start of the burst address generation operation and then the input signals to the first input terminals.
10. A semiconductor memory device including the burst address counter according to claim 7, comprising:
a memory cell array in which a plurality of memory cells are arrayed in a matrix;
a plurality of data buses through which data to be read/written from/in the memory cells propagate;
a read/write control circuit for controlling a data read/write from/in memory cells in said memory cell array, which correspond to two consecutive addresses, and parallelly processing the data between said read/write control circuit and said
plurality of data buses;
a memory cell selection circuit for selecting the memory cells in said memory cell array in accordance with the address signal containing the output signals representing a burst address output from said burst address counter;
a column transfer gate group controlled by said memory cell selection circuit to select a column in said memory cell array;
a first data line for outputting data read out from a plurality of memory cells selected when a predetermined column address signal bit of the address signal is at "0" through said column transfer gate group;
a second data line for outputting data read out from a plurality of memory cells selected when the predetermined column address signal bit is at "1" through said column transfer gate group;
a first sense amplifier for amplifying the data read out from the memory cells and a first data write circuit for writing data in the memory cells, said first sense amplifier and said first data write circuit being connected to said first data
line and having an active period controlled by a column address signal bit other than the predetermined column address signal bit;
a second sense amplifier for amplifying the data read out from the memory cells and a second data write circuit for writing data in the memory cells, said second sense amplifier and said second data write circuit being connected to said second
data line and having an active period controlled by the column address signal bit other than the predetermined column address signal bit;
a first data bus commonly connected to a plurality of sets of first sense amplifiers and first data write circuits having different active periods; and
a second data bus commonly connected to a plurality of sets of second sense amplifiers and second data write circuits having different active periods.
11. A semiconductor memory device according to claim 10,
wherein the memory cell comprises a static memory cell.
12. A semiconductor memory device comprising:
a memory cell array;
a burst address counter for generating a burst address signal as part of a column address signal for designating a column address of said memory cell array on the basis of external address signals; and
a circuit for selecting a memory cell in said memory cell array on the basis of the address signals and the burst address signal output from said burst address counter,
wherein said burst address counter comprises:
first multiplexer circuits each having first and second input terminals to receive an address signal at the second input terminal, select one of input signals input to the first and second input terminals, and output a first output signal
representing a burst address;
first register circuits for storing the first output signals output from said first multiplexer circuits, respectively;
first inverters for inverting the first output signals stored in said first register circuits and inputting the inverted output signals to the first input terminals of said first multiplexer circuits as input signals, respectively;
second multiplexer circuits each having first to third input terminals to receive a decoded address signal at the second input terminal, receive the address signal at the third input terminal, select one of input signals input to the first to
third input terminals, and output a second output signal representing the burst address;
second register circuits for storing the second output signals output from said second multiplexer circuits, respectively; and
second inverters for inverting the second output signals stored in said second register circuits and inputting the inverted output signals to the first input terminals of said second multiplexer circuits as input signals, respectively.
13. A burst address counter comprising:
first to fourth decoder circuits of a first group for decoding address signals;
first to fourth decoder circuits of a second group for decoding the address signals;
first to fourth multiplexer circuits of a first group each having first to third input terminals to receive decoded output signals from said first to fourth decoder circuit of the first group at the first input terminals, respectively, receive
the decoded output signals from said first to fourth decoder circuit of the second group at the second input terminals, respectively, and selectively output one of input signals to the first to third input terminals on the basis of a first multiplexer
control signal as output signals representing a burst address;
first to fourth multiplexer circuits of a second group each having first to third input terminals to selectively output one of input signals to the first to third input terminals on the basis of a second multiplexer control signal as output
signals to the third input terminals of the first to fourth multiplexer circuits of the first group, respectively;
first to fourth register circuits for storing the output signals from said first to fourth multiplexer circuits of the first group, respectively;
a first interconnection used in linear and interleave modes of single data rate scheme and connected to input an output signal from said first register circuit to the first input terminal of said fourth multiplexer circuit of the second group and
output signals from said second to fourth register circuits to the first input terminals of said first to third multiplexer circuits of the second group, respectively;
a second interconnection used in the interleave mode of single data rate scheme and connected to input the output signals from said first to third register circuits to the second input terminals of said second to fourth multiplexer circuits of
the second group, respectively, and the output signal from said fourth register circuit to the second input terminal of said first multiplexer circuit of the second group; and
first to fourth inverter circuits used in linear and interleave modes of double data rate scheme to invert the output signals from said first to fourth register circuits and input the inverted output signals to the third input terminals of said
first to fourth multiplexer circuits of the second group, respectively, as input signals.
14. A counter according to claim 13,
wherein each of said first to fourth multiplexer circuits of the first group selects one of an input signal to the first input terminal and an input signal to the second input terminal at the start of the burst address generation operation to
receive a start address, presets the start address in a corresponding one of said first to fourth register circuits, and then selects an input signal to the third input terminal, and
each of said first to fourth multiplexer circuits of the second group selects one of input signals to the first to third input terminals in accordance with a burst address generation mode.
15. A semiconductor memory device including the burst address counter according to claim 13, comprising:
a memory cell array in which a plurality of memory cells are arrayed in a matrix;
a plurality of data buses through which data to be read/written from/in the memory cells propagate;
a read/write control circuit for controlling a data read/write from/in memory cells in said memory cell array, which correspond to two consecutive addresses, and parallelly processing the data between said read/write control circuit and said
plurality of data buses;
a memory cell selection circuit for selecting the memory cells in said memory cell array in accordance with the address signal containing the output signals representing a burst address output from said burst address counter;
a column transfer gate group controlled by said memory cell selection circuit to select a column in said memory cell array;
a first data line for outputting data read out from a plurality of memory cells selected when a predetermined column address signal bit of the address signal is at "0" through said column transfer gate group;
a second data line for outputting data read out from a plurality of memory cells selected when the predetermined column address signal bit is at "1" through said column transfer gate group;
a first sense amplifier for amplifying the data read out from the memory cells and a first data write circuit for writing data in the memory cells, said first sense amplifier and said first data write circuit being connected to said first data
line and having an active period controlled by a column address signal bit other than the predetermined column address signal bit;
a second sense amplifier for amplifying the data read out from the memory cells and a second data write circuit for writing data in the memory cells, said second sense amplifier and said second data write circuit being connected to said second
data line and having an active period controlled by the column address signal bit other than the predetermined column address signal bit;
a first data bus commonly connected to a plurality of sets of first sense amplifiers and first data write circuits having different active periods; and
a second data bus commonly connected to a plurality of sets of second sense amplifiers and second data write circuits having different active periods.
16. A semiconductor memory device according to claim 15,
wherein the memory cell comprises a static memory cell.
17. A semiconductor memory device comprising:
a memory cell array;
a burst address counter for generating a burst address signal as part of a column address signal for designating a column address of said memory cell array on the basis of external address signals; and
a circuit for selecting a memory cell in said memory cell array on the basis of the address signals and the burst address signal output from said burst address counter,
wherein said burst address counter comprises:
first to fourth decoder circuits of a first group for decoding address signals;
first to fourth decoder circuits of a second group for decoding the address signals;
first to fourth multiplexer circuits of a first group each having first to third input terminals to receive decoded output signals from said first to fourth decoder circuit of the first group at the first input terminals, respectively, receive
the decoded output signals from said first to fourth decoder circuit of the second group at the second input terminals, respectively, and selectively output one of input signals to the first to third input terminals on the basis of a first multiplexer
control signal as output signals representing a burst address;
first to fourth multiplexer circuits of a second group each having first to third input terminals to selectively output one of input signals to the first to third input terminals on the basis of a second multiplexer control signal as output
signals to the third input terminals of the first to fourth multiplexer circuits of the first group, respectively;
first to fourth register circuits for storing the output signals from said first to fourth multiplexer circuits of the first group, respectively;
a first interconnection used in linear and interleave mode of single data rate scheme and connected to input an output signal from said first register circuit to the first input terminal of said fourth multiplexer circuit of the second group and
output signals from said second to fourth register circuits to the first input terminals of said first to third multiplexer circuits of the second group, respectively;
a second interconnection used in the interleave mode of single data rate scheme and connected to input the output signals from said first to third register circuits to the second input terminals of said second to fourth multiplexer circuits of
the second group, respectively, and the output signal from said fourth register circuit to the second input terminal of said first multiplexer circuit of the second group; and
first to fourth inverter circuits used in linear and interleave modes of double data rate scheme to invert the output signals from said first to fourth register circuits and input the inverted output signals to the third input terminals of said
first to fourth multiplexer circuits of the second group, respectively, as input signals.
18. A burst address counter comprising:
multiplexer circuits each having first and second input terminals to selectively output one of inputs to the first and second input terminals on the basis of a multiplexer control signal;
register circuits storing output signals from said multiplexer circuits, respectively;
inverter circuits for inverting output signals from said register circuits and inputting the inverted output signals to the first input terminals of said multiplexer circuits, respectively; and
decoder circuits for decoding address signals and inputting the decoded address signals to the second input terminals of some of said multiplexer circuits, respectively.
19. A semiconductor memory device including the burst address counter according to claim 18, comprising:
a memory cell array in which a plurality of memory cells are arrayed in a matrix;
a plurality of data buses through which data to be read/written from/in the memory cells propagate;
a read/write control circuit for controlling a data read/write from/in memory cells in said memory cell array, which correspond to two consecutive addresses, and parallelly processing the data between said read/write control circuit and said
plurality of data buses;
a memory cell selection circuit for selecting the memory cells in said memory cell array in accordance with the address signal containing the output signals representing a burst address output from said burst address counter;
a column transfer gate group controlled by said memory cell selection circuit to select a column in said memory cell array;
a first data line for outputting data read out from a plurality of memory cells selected when a predetermined column address signal bit of the address signal is at "0" through said column transfer gate group;
a second data line for outputting data read out from a plurality of memory cells selected when the predetermined column address signal bit is at "1" through said column transfer gate group;
a first sense amplifier for amplifying the data read out from the memory cells and a first data write circuit for writing data in the memory cells, said first sense amplifier and said first data write circuit being connected to said first data
line and having an active period controlled by a column address signal bit other than the predetermined column address signal bit;
a second sense amplifier for amplifying the data read out from the memory cells and a second data write circuit for writing data in the memory cells, said second sense amplifier and said second data write circuit being connected to said second
data line and having an active period controlled by the column address signal bit other than the predetermined column address signal bit;
a first data bus commonly connected to a plurality of sets of first sense amplifiers and first data write circuits having different active periods; and
a second data bus commonly connected to a plurality of sets of second sense amplifiers and second data write circuits having different active periods.
20. A semiconductor memory device according to claim 19,
wherein the memory cell comprises a static memory cell.
21. A semiconductor memory device comprising:
a memory cell array;
a burst address counter for generating a burst address signal as part of a column address signal for designating a column address of said memory cell array on the basis of external address signals; and
a circuit for selecting a memory cell in said memory cell array on the basis of the address signals and the burst address signal output from said burst address counter,
wherein said burst address counter comprises:
multiplexer circuits each having first and second input terminals to selectively output one of inputs to the first and second input terminals on the basis of a multiplexer control signal;
register circuits storing output signals from said multiplexer circuits, respectively;
inverter circuits for inverting output signals from said register circuits and inputting the inverted output signals to the first input terminals of said multiplexer circuits, respectively; and
decoder circuits for decoding address signals and inputting the decoded address signals to the second input terminals of some of said multiplexer circuits, respectively. |
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Claims |
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Description |
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BACKGROUND OF
THE INVENTION
The present invention relates to a semiconductor memory device and an address counter for generating an internal address signal for the device and, more particularly, to a synchronous semiconductor memory device operating in synchronism with an
external clock input and having an operation mode in which a burst address signal is generated by itself in the memory chip on the basis of an externally supplied address signal to perform a read/write.
The present invention also relates to a burst address counter for generating a burst address signal, which is used for, e.g., an SRAM (Static RAM) having an operation mode in which a plurality of data buses are used to parallelly process data for
a plurality of addresses.
In a conventional semiconductor memory, when only a normal synchronous operation mode is required, an operation mode of single data rate (SDR) scheme is supported, in which 1-bit data per input/output terminal is read/written from/in a memory
cell in synchronism with only the rise of an external clock input.
As one of high-speed semiconductor memory operation schemes, a burst mode operation has been proposed. In this burst mode operation, a burst address is generated by itself in the chip on the basis of an externally supplied address signal in
synchronism with a clock signal to perform a read/write.
To generate a burst address, consecutive addresses are generated in accordance with predetermined regularity (linear mode or interleave mode) on the basis of a 1- or 2-bit burst address signal.
In the burst mode period, if the burst address signal is assigned to two lower bits A1 and A0 of, e.g., an 18-bit address signal, the 16 upper address signal bits other than the address signal bits are kept fixed.
In the linear or interleave mode, a lower bit of a burst address signal alternately has a value 0, 1, 0, 1, . . . (or 1, 0, 1, 0, . . . ) without repeating the same value.
A burst address is often assigned to lower bits of a column address of a memory cell because it is required to quickly switch the memory cell to be selected.
A column system for selecting a column has a larger margin in terms of timing than that of a row system for selecting a word line of a cell. For this reason, the entire operation speed can be increased by assigning a burst address which takes a
time to generate to the column system.
In the following description and drawing, column address bits Y1 and Y0 correspond to the burst address bits A1 and A0, respectively.
Such a burst mode operation can be applied not only to the SDR operation mode but also to an operation mode of double data rate (DDR) scheme in which data is read/written in synchronism with the up-edge (rise) and down-edge (fall) of an external
clock input.
For a memory having the DDR operation mode, the internal operation speed does not particularly increase. When data is read or written in synchronism with both the rise and fall of an external clock input at only an I/O buffer, the internal
operation speed of the memory appears to double (data read/write rate doubles) when viewed outside the memory. As such a memory, an SRAM has been proposed.
In an SRAM having the DDR operation mode, data corresponding to a plurality of addresses are parallelly processed using a plurality of data buses. The internal operation itself such as an actual data write in a memory cell is performed at the
same speed (frequency) as that of an external clock input. However, the data transfer rate is doubled by parallelly processing data corresponding to two addresses at once.
That is, in the SRAM having the DDR operation mode, the data bus in the memory is doubled, and cells designated by two consecutive addresses of a burst address are simultaneously selected for a write or read.
Many SRAMs having the DDR operation mode can select either the above-described DDR operation mode or SDR operation mode.
A method of generating a burst address will be described with reference to FIGS. 1 to 4.
(1) In the linear mode of SDR scheme, by a binary count-up operation from an external address input as a start address, the start address is sequentially incremented to change the burst address.
More specifically, as shown in FIG. 1, when the start address is (0, 0), the burst address changes in the order of (0, 0).fwdarw.(0, 1).fwdarw.(1, 0).fwdarw.(1, 1). When the start address is (0, 1), the burst address changes in the order of (0,
1).fwdarw.(1, 0).fwdarw.(1, 1).fwdarw.(0, 0). When the start address is (1, 0), the burst address changes in the order of (1, 0).fwdarw.(1, 1).fwdarw.(0, 0).fwdarw.(0, 1). When the start address is (1, 1), the burst address changes in the order of (1,
1).fwdarw.(0, 0).fwdarw.(0, 1).fwdarw.(1, 0).
(2) In the interleave mode of SDR scheme, a signal obtained by performing the binary count-up operation from the external address input as a start address to increment the start address is exclusively ORed with the external address input, so the
burst address changes from the start address as shown in FIG. 2.
(3) In the linear mode of DDR scheme, as shown in FIG. 3, an address in the above-described linear mode of SDR scheme and an adjacent address, i.e., two consecutive address signals are paired and sequentially incremented from the start address to
progress the burst address.
(4) In the interleave mode of DDR scheme, as shown in FIG. 4, an address in the above-described interleave mode of SDR scheme and an adjacent address, i.e., two consecutive address signals are paired and sequentially incremented from the start
address to progress the burst address.
To generate a burst address signal in the linear mode, an arrangement shown in FIG. 5 can be used.
Of signal bits of an external address input, the signal bits A0 and A1 corresponding to each other are input to first and second registers 61 and 62, respectively, in synchronism with an external clock signal CK. The outputs from the registers
61 and 62 are input to first and second binary counters 63 and 64, respectively, in correspondence with each other.
In this case, the first binary counter 63 counts signal bits in synchronism with the rise of the external clock signal CK. The second binary counter 64 counts signal bits in synchronism with the rise of a clock signal 2.times.CK having a speed
twice that of the external clock signal CK. A 2-bit count-up operation is performed by the two binary counters 63 and 64.
A 4-bit signal consisting of a 2-bit complementary signal output from the first binary counter 63 and a 2-bit complementary signal output from the second binary counter 64 is input to a decoder 65 as a NAND circuit group to generate four column
decode signal bits Ac1 to Ac4.
However, as described above, operating the second binary counter 64 at a speed twice that of the external clock signal CK poses a problem of operation speed as the speed of clock signal CK increases, and therefore is inappropriate for increasing
the memory operation speed.
The binary counter 63 or 64 uses, as the most common structure, a toggle (T) flip-flop (F/F) as shown in FIG. 6. The number of NAND gates used therefor is as large as six. Generation of a burst address signal is delayed due to the gate delay,
and consequently, the memory operation speed (e.g., access time) is limited.
When the burst address counter is to generate a burst address signal in the interleave mode, an exclusive OR circuit is added to the output side of the arrangement as shown in FIG. 6 to perform exclusive OR between the address signal and the
external address input. For this purpose, more gates are used in addition to the T F/F shown in FIG. 6. Generation of a burst address signal is delayed due to the gate delay, and consequently, the memory operation speed (e.g., access time) is limited.
As described above, in the burst address counter using the conventionally available binary counters, the number of elements used to generate a burst address signal in the linear mode of SDR scheme is large. Generation of the burst address signal
is delayed due to the gate delay, and the memory operation speed is limited.
The number of elements used to generate a burst address signal in the interleave mode of SDR scheme is larger, so the memory operation speed is further limited.
To generate a burst address signal to selectively cope with the linear or interleave mode of SDR scheme, a logic gate must be added, resulting in more complex circuit arrangement. The number of elements to be used further increases to limit the
memory operation speed.
To generate a burst address signal in the linear or interleave mode to selectively cope with the DDR operation mode or SDR operation mode of the burst address counter 2, the above-described problem becomes very serious.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made to solve the above problem, and has as its object to provide a semiconductor memory device having a simple circuit arrangement and excellent high-speed operability and capable of selectively generating the
linear or interleave mode of SDR scheme, and a burst address counter therefor.
It is another object of the present invention to provide a synchronous semiconductor memory device realized by a relatively simple circuit arrangement and capable of selectively generating a burst address signal in the linear or interleave mode
of DDR scheme and increasing the memory operation speed, and a burst address counter therefor.
It is still another object of the present invention to provide a synchronous semiconductor memory device realized by a relatively simple circuit arrangement and capable of selectively generating a burst address signal in the linear or interleave
mode to selectively cope with the DDR operation mode or SDR operation mode and increasing the memory operation speed, and a burst address counter therefor.
In order to achieve the above objects, according to the first aspect of the present invention, there is provided a burst address counter comprising:
first to fourth decoder circuits for decoding address signals;
first to fourth multiplexer circuits having first to third input terminals to receive the decoded address signals output from the first to fourth decoder circuits from the first input terminals, respectively, and selectively output one of input
signals input to the first to third input terminals on the basis of a control signal;
first to fourth register circuits for storing output signals representing a burst address and output from the first to fourth multiplexer circuits, respectively;
a first interconnection used in linear and interleave modes of single data rate scheme and connected to input the output signal stored in the first register circuit to the second input terminal of the fourth multiplexer circuit and the output
signals stored in the second to fourth register circuits to the second input terminals of the first to third multiplexer circuits, respectively; and
a second interconnection used in the interleave mode of single data rate scheme and connected to input the output signals stored in the first to third register circuits to the third input terminals of the second to fourth multiplexer circuits,
respectively, and the output signal stored in the fourth register circuit to the third input terminal of the first multiplexer circuit.
According to the second aspect of the present invention, there is provided a burst address counter comprising:
first multiplexer circuits each having first and second input terminals to receive an address signal from the second input terminal, select one of input signals input to the first and second input terminals, and output a first output signal
representing a burst address;
first register circuits for storing the first output signals output from the first multiplexer circuits, respectively;
inverters for inverting the first output signals stored in the first register circuits and inputting the inverted output signals to the first input terminals of the first multiplexer circuits as input signals, respectively;
second multiplexer circuits each having first to third input terminals to receive the decoded address signal from the second input terminal, receive the address signal from the third input terminal, select one of input signals input to the first
to third input terminals, and output a second output signal representing a burst address;
second register circuits for storing the second output signals output from the second multiplexer circuits, respectively; and
inverters for inverting the second output signals stored in the second register circuits and inputting the inverted output signals to the first input terminals of the second multiplexer circuits as input signals, respectively.
According to the third aspect of the present invention, there is provided a burst address counter comprising:
first to fourth decoder circuits of a first group for decoding address signals;
first to fourth decoder circuits of a second group for decoding address signals;
first to fourth multiplexer circuits of a first group each having first to third input terminals to receive decoded output signals from the first to fourth decoder circuit of the first group from the first input terminals, respectively, receive
the decoded output signals from the first to fourth decoder circuit of the second group from the second input terminals, respectively, and selectively output one of input signals to the first to third input terminals on the basis of a first multiplexer
control signal as output signals representing a burst address;
first to fourth multiplexer circuits of a second group each having first to third input terminals to selectively output one of input signals to the first to third input terminals on the basis of a second multiplexer control signal as output
signals to the third input terminals of the first to fourth multiplexer circuits of the first group, respectively;
first to fourth register circuits for storing the output signals from the first to fourth multiplexer circuits of the first group, respectively;
a first interconnection used in linear and interleave modes of single data rate scheme and connected to input an output signal from the first register circuit to the first input terminal of the fourth multiplexer circuit of the second group and
output signals from the second to fourth register circuits to the first input terminals of the first to third multiplexer circuits of the second group, respectively;
a second interconnection used in the interleave mode of single data rate scheme and connected to input the output signals from the first to third register circuits to the second input terminals of the second to fourth multiplexer circuits of the
second group, respectively, and the output signal from the fourth register circuit to the second input terminal of the first multiplexer circuit of the second group; and
first to fourth inverter circuits used in linear and interleave modes of double data rate scheme to invert the output signals from the first to fourth register circuits and input the inverted output signals to the third input terminals of the
first to fourth multiplexer circuits of the second group, respectively, as input signals.
According to the fourth aspect of the present invention, there is provided a burst address counter comprising:
multiplexer circuits each having first and second input terminals to selectively output one of inputs to the first and second input terminals on the basis of a multiplexer control signal;
register circuits storing output signals from the multiplexer circuits, respectively;
inverter circuits for inverting output signals from the register circuits and inputting the inverted output signals to the first input terminals of the multiplexer circuits, respectively; and
decoder circuits for decoding address signals and inputting the decoded address signals to the second input terminals of some of the multiplexer circuits, respectively.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention
may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of
the preferred embodiments given below, serve to explain the principles of the invention.
FIG. 1 is a view for explaining the change rule of a burst address signal in the linear mode of SDR scheme;
FIG. 2 is a view for explaining the change rule of a burst address signal in the interleave mode of SDR scheme;
FIG. 3 is a view for explaining the change rule of a burst address signal in the linear mode of DDR scheme;
FIG. 4 is a view for explaining the change rule of a burst address signal in the interleave mode of DDR scheme;
FIG. 5 is a circuit diagram showing a circuit for generating a burst address signal in the linear mode as a burst address signal for a conventional synchronous SRAM;
FIG. 6 is a circuit diagram showing a toggle (T) flip-flop (F/F) as the most common structure of a binary counter shown in FIG. 1;
FIG. 7 is a block diagram schematically showing the overall arrangement of a synchronous SRAM according to the first embodiment of the present invention;
FIG. 8 is a circuit diagram showing the connection relationship among column transfer gates, data lines, sense amplifiers/data write circuits, and data buses corresponding to some cell portions of a memory cell array shown in FIG. 7;
FIG. 9 is a circuit diagram showing a first data bus switching circuit and data output control circuit in a data input/output circuit shown in FIG. 7;
FIGS. 10A and 10B are circuit diagrams showing two forms in which the first data bus switching circuit shown in FIG. 9 controls data transfer routes in the SDR operation mode;
FIGS. 11A and 11B are circuit diagrams showing two forms in which the first data bus switching circuit shown in FIG. 9 controls data transfer routes in the DDR operation mode;
FIG. 12 is a circuit diagram showing a second data bus switching circuit and data input control circuit in the data input/output circuit shown in FIG. 7;
FIGS. 13A, 13B, and 13C are circuit diagrams showing a form in which the second data bus switching circuit shown in FIG. 12 controls data transfer routes in the SDR operation mode and two forms in which the second data bus switching circuit
controls data transfer routes in the DDR operation mode;
FIG. 14 is a circuit diagram showing a case in which a burst address signal in the linear or interleave mode of SDR scheme is generated by a burst address counter shown in FIG. 7;
FIG. 15 is a timing chart showing a data shift operation in the linear mode when the start address is, e.g., (0, 0) in the circuit shown in FIG. 14;
FIG. 16 is a timing chart showing a data shift operation in the interleave mode when the start address is, e.g., (1, 1) in the circuit shown in FIG. 14;
FIG. 17 is a timing chart showing a data read operation in the SDR operation mode when the synchronous SRAM shown in FIG. 7 uses the burst address counter shown in FIG. 14;
FIG. 18 is a circuit diagram showing a case in which the burst address counter shown in FIG. 7 generates a burst address signal in the linear or interleave mode of DDR scheme;
FIG. 19 is a timing chart showing the data shift operation in the linear mode when the start address is (0, 0) in the circuit shown in FIG. 18;
FIG. 20 is a timing chart showing the data shift operation in the interleave mode when the start address is (1, 1) in the circuit shown in FIG. 18;
FIG. 21 is a timing chart showing a data read operation in the DDR operation mode when the synchronous SRAM shown in FIG. 7 uses the burst address counter shown in FIG. 18; and
FIG. 22 is a circuit diagram showing a case in which a burst address signal in the linear or interleave mode of SDR or DDR scheme is selectively generated by the burst address counter shown in FIG. 7.
DETAILED DESCRIPTION OF THE INVENTION
The embodiments of the present invention will be described below in detail with reference to the accompanying drawing.
FIG. 7 is a block diagram schematically showing the overall arrangement of a synchronous SRAM according to the first embodiment and capable of selecting a DDR or SDR operation mode.
Referring to FIG. 7, reference symbols A0 to A17 denote least to most significant bits of an address signal. Reference numeral 1 denotes a pre-decoder for receiving 15 upper bits A17 to A2 of the address signal bits A0 to A17 and pre-decoding
these address bits; 2, a burst address counter for receiving two lower bits A1 and A0, assigned as a burst address signal, of, e.g., nine column address signal bits A8 to A0 of the burst address signal bits A0 to A17; 15, an address register for
receiving the output from the pre-decoder; 3, an address decoder for receiving the output from the address register 15 and the output from the burst address counter 2; 4, a memory cell array; 5, a row selection circuit for selecting rows of the memory
cell array 4 in accordance with a row decoding output from the address decoder 3; 6, a column selection circuit as a column transfer gate group ON/OFF-controlled to select columns of the memory cell array 4 in accordance with the column decoding output
from the address decoder 3; 7, a sense amplifier/data write circuit; 81, a first data bus; 82, a second data bus; and 9, a data input/output circuit.
A read/write control circuit 14 controls a data read/write from/in a memory cell of the memory cell array 4 in correspondence with a selected address and transfers data to the plurality of data buses 81 and 82.
The operation mode of the SRAM shown in FIG. 7 is controlled by causing a command decoder 10 to decode three control signals input from, e.g., three external terminals 11 to 13. For example, the start/stop of the burst operation is controlled in
accordance with the logic level of a first control signal START/STOP, the read/write operation is controlled in accordance with the logic level of a second control signal READ/WRITE, and the DDR or SDR operation mode is selected in accordance with the
logic level of a third control signal DOUBLE/SINGLE.
The pre-decoder 1 decodes, of the nine column address signal bits A8 to A0, seven bits A8 to A2 except the two lower bits A1 and A0 assigned as a burst address signal while dividing them into, e.g., three groups.
The burst address counter 2 generates a burst address signal whose start address is determined on the basis of the contents of the two input signal bits A1 and A0 in correspondence with the operation mode described above with reference to FIGS. 1
to 4. A specific example will be described later.
The memory cell array 4 is constituted by a memory cell group in which memory cells are arrayed in a two-dimensional matrix in correspondence with intersections between a plurality of word lines and bit lines. Each memory cell is a static memory
cell (SRAM cell) for storing complementary data in a pair of storage nodes and transmitting/receiving data to/from a data line pair. As is well known, the SRAM cell has an NMOS transistor pair for sense drive, a PMOS transistor pair for load, and an
NMOS transistor pair for data transfer gates.
FIG. 8 schematically shows an example of the connection relationship among column transfer gates TG, data lines DL1 and DL2, sense amplifiers S/A and data write circuits Din, and data buses corresponding to some cell portions of the memory cell
array 4 in the synchronous SRAM shown in FIG. 7.
In the cell portions, four | | |
