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Claims  |
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I claim:
1. A memory system comprising:
a memory chip;
a CPU for controlling read/write of data from/in said memory chip; and
a bus for exchanging data between said memory chip and said CPU,
wherein said memory chip comprises:
a memory cell array;
a spare memory cell;
a fuse section for, when a failure occurs in a memory cell of said memory cell array, replacing said failure-memory cell with said spare memory cell;
a read/write section for reading/writing data from/in said memory cell array in response to an address and a command supplied from said CPU;
an input section for supplying data from said CPU via said bus to said read/write section;
an output section for supplying data read out from said memory cell array by said read/write section to said CPU via said bus;
an internal clock generation section for generating an internal clock from an external clock supplied from said CPU, and controlling said read/write section; said input section, and said output section on the basis of the internal clock; and
a fuse program section for programming a failure-address in said fuse section on the basis of a fuse program signal supplied from said CPU,
wherein, after said CPU writes data in a memory cell of said memory cell array, the data is read out and subject to verification, in the case of incoincidence, said CPU supplies the fuse program signal to said fuse program section, said fuse
program section programs the failure-address in said fuse section, and a memory cell in which a failure has occurred is replaced with said spare memory cell on the basis of the address programmed in said fuse section.
2. A system according to claim 1, wherein said internal clock generation section comprises:
a clock buffer for generating the internal clock on the basis of the external clock supplied from said CPU, and supplying the internal clock to said read/write circuit; and
a synchronous circuit for eliminating a skew of the internal clock output from said clock buffer with respect to the external clock, and outputting the internal clock from which the skew is eliminate to said input section and said output section.
3. A system according to claim 1,
wherein the memory cell array has a plurality of memory cell arrays in which memory cells are laid out in a matrix form, and the system further comprises:
row decoders arranged in correspondence with said plurality of memory cell arrays to select a row of each of said memory cell arrays on the basis of a row address signal;
sense amplifier circuits arranged in correspondence with said plurality of memory cell arrays to receive data read out from memory cells on the row selected by said row decoders;
DQ lines which are arranged in correspondence with said sense amplifier circuits, and commonly used in said plurality of memory cell arrays;
column switches arranged in correspondence with said sense amplifier circuits to select sense amplifier circuits to be connected to said DQ lines on the basis of a column address signal;
a plurality of DQ decoders for performing a selection operation for said DQ lines on the basis of the column address signal for each I/O;
a plurality of DQ buffers arranged in correspondence with said DQ decoders to receive data on DQ lines selected by said DQ decoders for each I/O;
a spare DQ line commonly used by said DQ lines belonging to respective I/Os;
a spare sense amplifier circuit which receives data read out from a spare memory cell;
a spare column switch for selecting connection of said spare sense amplifier circuit to said spare DQ line;
a first storage section for storing an address of a DQ line in which a failure has occurred; and
a second storage section, arranged for each I/O, for storing an I/O to which the failure-DQ line belongs,
wherein, when the address stored in said first storage section is accessed, said DQ line belonging to the I/O stored in said second storage section and having the address stored in said first storage section, a sense amplifier circuit connected
to said DQ line, and a column switch selecting said sense amplifier circuit are respectively replaced with said spare DQ line, said spare sense amplifier circuit, and said spare column switch, and said spare DQ line, said spare sense amplifier circuit,
and said spare column switch are commonly used by said DQ lines belonging to respective I/Os.
4. A system according to claim 1,
wherein the memory cell array has a plurality of memory cell arrays in which memory cells are laid out in a matrix form, and the system further comprises:
row decoders arranged in correspondence with said plurality of memory cell arrays to select a row of each of said memory cell arrays on the basis of a row address signal;
sense amplifier circuits arranged in correspondence with said plurality of memory cell arrays to receive data read out from memory cells on the row selected by said row decoders;
DQ lines which are arranged in correspondence with said sense amplifier circuits, and commonly used in said plurality of memory cell arrays;
column switches arranged in correspondence with said sense amplifier circuits to select sense amplifier circuits to be connected to said DQ lines on the basis of a column address signal;
a plurality of DQ decoders for performing a selection operation for said DQ lines on the basis of the column address signal for each I/O;
a plurality of DQ buffers arranged in correspondence with said DQ decoders to receive data on DQ lines selected by said DQ decoders for each I/O;
a spare DQ line commonly used by said DQ lines belonging to respective I/Os;
a plurality of spare sense amplifier circuits which receive data read out from a spare memory cell;
a spare column switch for selecting connection of said plurality of spare sense amplifier circuits to said spare DQ line;
a first detection section, arranged in correspondence with said plurality of spare sense amplifier circuits, for storing an address of a DQ line in which a failure has occurred, and detecting access to the stored address;
a second detection section for storing, for each I/O, information on whether a DQ line having the accessed address must be replaced, and when said first detection section detects the access to the address, detecting, for each I/O, said DQ line
having the accessed address which must be replaced on the basis of the information; and
a switching section for switching a data path extending to a DQ buffer corresponding to said DQ line which must be replaced from said DQ line which must be replaced and detected by said second detection section, to a data path extending from said
spare DQ line to said DQ buffer corresponding to said DQ line which must be replaced for each of said spare sense amplifier circuits when said second detection section detects that said DQ line must be replaced.
5. A system according to claim 1,
wherein the memory cell array has a plurality of memory cell arrays in which memory cells are laid out in a matrix form, and the system further comprises:
row decoders arranged in correspondence with said plurality of memory cell arrays to select a row of each of said memory cell arrays on the basis of a row address signal;
sense amplifier circuits arranged in correspondence with said plurality of memory cell arrays to receive data read out from memory cells on the row selected by said row decoders;
DQ lines which are arranged in correspondence with said sense amplifier circuits, and commonly used in said plurality of memory cell arrays;
column switches arranged in correspondence with said sense amplifier circuits to select sense amplifier circuits to be connected to said DQ lines on the basis of a column address signal;
a plurality of DQ decoders for performing a selection operation for said DQ lines on the basis of the column address signal for each I/O;
a plurality of DQ buffers arranged in correspondence with said DQ decoders to receive data on DQ lines selected by said DQ decoders for each I/O;
a spare DQ line commonly used by said DQ lines belonging to respective I/Os;
a plurality of spare sense amplifier circuits which receive data read out from a spare memory cell;
a spare column switch for selecting connection of said plurality of spare sense amplifier circuits to said spare DQ line;
a first detection section, arranged in correspondence with said plurality of spare sense amplifier circuits, for storing an address of a DQ line in which a failure has occurred, and detecting access to the stored address;
a second detection section for storing, for each I/O, information on whether a DQ line having the accessed address must be replaced, and when said first detection section detects the access to the address, detecting, for each I/O, said DQ line
having the accessed address which must be replaced on the basis of the information;
a third detection section for detecting access to a memory cell array to be replaced; and
a switching section for switching a data path extending to a DQ buffer corresponding to said DQ line of said memory cell array to be replaced that is detected by said second detection section, to a data path extending from said spare DQ line to
said DQ buffer corresponding to said DQ line which must be replaced for each of said spare sense amplifier circuits when said second detection section detects said DQ line, and said third detection section detects the access.
6. A redundancy method in a memory system, wherein said memory system comprises:
a memory chip;
a CPU for controlling read/write of data from/in said memory chip; and
a bus for exchanging data between said memory chip and said CPU,
wherein said memory chip comprises:
a memory cell array;
a spare memory cell;
a fuse section for, when a failure occurs in a memory cell of said memory cell array, replacing said failure-memory cell with said spare memory cell;
a read/write section for reading/writing data from/in said memory cell array in response to an address and a command supplied from said CPU;
an input section for supplying data from said CPU via said bus to said read/write section;
an output section for supplying data read out from said memory cell array by said read/write section to said CPU via said bus;
an internal clock generation section for generating an internal clock from an external clock supplied from said CPU, and controlling said read/write section, said input section, and said output section on the basis of the internal clock; and
a fuse program section for programming a failure-address in said fuse section on the basis of a fuse program signal supplied from said CPU,
the redundancy method in said memory system, comprising:
the first step of writing data from said CPU via said bus in said memory chip;
the second step of reading out the written data from said memory chip to said CPU via said bus;
the third step of causing said CPU to verify the data written in said memory chip in the first step with the data read out from said memory chip in the second step; and
the fourth step of, when incoincidence between the two data is detected in the third step, supplying the fuse program signal from said CPU to said fuse program section, and programming a failure-address in said fuse section.
7. A method according to claim 6, wherein the first to fourth steps are repeatedly executed for each memory cell in said memory cell array.
8. A method according to claim 6, further comprising between the third and fourth steps:
the fifth step of checking the number of usable fuse section,
wherein, in the fifth step, if that usable fuse section is detected, the fourth step is executed to program the failure-address in said fuse section, and if that no usable fuse section is left is detected, a system failure is determined to stop
redundancy.
9. A method according to claim 7, further comprising between the third and fourth steps:
the fifth step of checking the number of usable fuse section,
wherein, in the fifth step, if that usable fuse section is left is detected, the fourth step is executed to program the failure-address in aid fuse section, and if that no usable fuse section is left is detected, a system failure is determined to
stop redundancy. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a memory system using the same and, more particularly, to a redundancy system and method for remedying a failure.
More specifically, the present invention relates to an address identification system and method for identifying an address having undergone spare replacement in a multi-bit memory or the like for inputting/outputting data parallel.
For a large memory capacity, it is becoming important to simultaneously exchange a plurality of data with the memory upon reception of an address in order to effectively utilize the capacity. That is, the memory must have a multi-bit
arrangement.
As the data amount which can be simultaneously exchanged increases, the data transfer efficiency increases to effectively utilize the capacity of the memory serving as a high-speed data transfer memory. At this time, the address spaces of bits
simultaneously transferred are the same, and cannot be externally discriminated by addresses. In other words, the addresses of simultaneously input/output data are completely the same, and identified by only different I/Os outside the memory.
If the capacity of the memory becomes larger, the memory is manufactured by an advanced micropatterning technique. The non-defective ratio of memories as products, i.e., the yield greatly depends on the presence of dust and particles in the
manufacturing process, the fluctuation of the manufacturing process, or the like.
Accordingly, the ratio of non-defectives in which all memory cells serving as data storage locations are perfect is naturally low. For this reason, the yield must be increased by a redundancy technique of arranging a redundancy memory cell in
advance in addition to a memory cell having an originally necessary capacity, replacing a memory cell in which a failure occurs with the redundancy memory cell, and remedying the failure-memory cell.
FIG. 1 is a block diagram showing a conventional multi-bit memory. Memory cell arrays 11-1 to 11-n in which memory cells are laid out in an array have row decoders 12-1 to 12-n, sense amplifiers 13-1 to 13-n, and column switches 14-1 to 14-n,
respectively.
When a row address signal is supplied to the row decoders 12-1 to 12-n, data of memory cells on selected rows in the memory cell arrays 11-1 to 11-n are sensed, amplified, and then latched by the sense amplifiers 13-1 to 13-n.
The sense amplifiers 13-1 to 13-n are commonly connected to DQ lines 15 via the column switches 14-1 to 14-n in units of columns.
A column address signal is supplied to the column switches 14-1 to 14-n and a DQ decoder 16. The column switches 14-1 to 14-n perform selection operations for the sense amplifiers 13-1 to 13-n to determine the connection relationship between the
sense amplifiers and the DQ lines 15 in accordance with the column address signal.
The data latched by the selected sense amplifiers are read onto the DQ lines 15. The DQ decoder 16 performs a selection operation for the DQ lines 15. The data read onto the DQ lines 15 selected by the DQ decoder 16 are output via DQ buffers
(DQB) 17-1 to 17-m.
Alternatively, write data input to the DQ buffers 17-1 to 17-m are selectively written in memory cells in the memory cell arrays 11-1 to 11-n via the DQ lines 15 selected by the DQ decoder 16, the corresponding column switches 14-1 to 14-n, and
the corresponding sense amplifiers 13-1 to 13-n. The I/O to which a specific DQ line 15 belongs is fixed.
FIG. 2 schematically shows an example of how to take column redundancy in the multi-bit memory having this arrangement. FIG. 2 shows only an extracted portion related to decoding by the column address signal in FIG. 1.
Since a column address signal is supplied outside the memory to select a column, this column address signal is used to specify a failure-column and replace it with a spare column.
DQ lines common to the memory cell arrays 11-1 to 11-n are called over-laid DQ lines 15a. The respective pairs of over-laid DQ line 15a are selectively connected to sense amplifier circuits 13a each having four sense amplifiers via column
switches 14a.
Eight pairs of over-laid DQ lines 15a have one pair of spare DQ lines 15b. The spare DQ lines 15b are connected to a spare sense amplifier circuit 13b having four spare amplifiers via a spare column switch 14b.
If a failure-column belongs to any one of the eight pairs of DQ lines 15a, the pair of DQ lines are entirely replaced with the pair of spare DQ lines 15b. The eight pairs of DQ lines 15a and one pair of spare DQ lines 15b belong to one I/O, and
are selectively connected to each of the DQ buffers 17-1, 17-2, . . . via a corresponding one of DQ decoders 16-1, 16-2, . . .
The DQ buffers 17-1, 17-2, . . . are respectively connected to RWD (read/write data) buses 18-1, 18-2, . . . to output/input I/O data outside the memory.
A fuse box 19 is constituted by a 4-bit circuit, i.e., a 1-bit fuse circuit 19a representing whether the spare DQ lines 15b are used, and 3-bit fuse circuits 19b, 19c, and 19d representing a failure-one of the eight pairs of over-laid DQ lines
15a.
The address of the failure-DQ line is designated in the fuse circuits 19b, 19c, and 19d. When the bits of a column address signal corresponding to the failure-DQ line coincide with the three bits, the DQ decoders 16-1, 16-2, . . . are switched
to select the spare DQ lines 15b.
In general, each of the fuse circuits 19a to 19d constituting the fuse bits has a fuse element, which is fused and programmed by a current, a laser beam, or the like.
In the above arrangement, however, even when a spare must be used at only one I/O, the lines having the same address are also replaced with spares at all other I/Os.
No problem arises when the number of I/Os is small, and the number of DQ lines belonging to one I/O is large. However, as the number of bits increases, the number of spares increases, and spares are unnecessarily replaced simultaneously. For
this reason, the above-described multi-bit memory redundancy system and method are wasteful.
In various systems using a semiconductor memory device with the above arrangement, when a failure occurs in a memory cell due to a deterioration over time or the like, the redundancy technique cannot be applied upon incorporating the memory
device into the system.
As described above, the conventional semiconductor memory device is inefficient for failure remedy.
The redundancy system and method in the conventional multi-bit memory are wasteful and inefficient.
By the address identification system and method in the conventional multi-bit memory, an address in the multi-bit memory cannot be identified for each I/O, and spare replacement is inefficient.
In the conventional memory system and its redundancy method, when a failure occurs in a memory cell due to a deterioration over time or the like, the redundancy technique cannot be applied upon incorporating the memory cell into the system, and
the failure of the memory cell becomes the failure of the whole system.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation, and has as its object to provide a semiconductor memory device in which a failure can be efficiently remedied.
It is another object of the present invention to provide a redundancy system and method capable of efficiently remedying a failure even for a larger number of bits.
It is still another object of the present invention to provide an address identification system and method capable of identifying an address in a multi-bit memory for each I/O, and efficiently performing spare replacement.
It is still another object of the present invention to provide a memory system and its redundancy system in which, even when a failure occurs in a memory cell due to a deterioration over time or the like, the memory cell can be remedied even upon
incorporating the memory cell into the system.
To achieve these objects, according to the first aspect of the present invention, there is provided a semiconductor memory device comprising
a plurality of memory cell arrays in which memory cells are laid out in a matrix form,
row decoders arranged in correspondence with the plurality of memory cell arrays to select a row of each of the memory cell arrays on the basis of a row address signal,
sense amplifier circuits arranged in correspondence with the plurality of memory cell arrays to receive data read out from memory cells on the row selected by the row decoders,
DQ lines which are arranged in correspondence with the sense amplifier circuits, and commonly used in the plurality of memory cell arrays,
column switches arranged in correspondence with the sense amplifier circuits to select sense amplifier circuits to be connected to the DQ lines on the basis of a column address signal,
a plurality of DQ decoders for performing a selection operation for the DQ lines on the basis of the column address signal for each I/O,
a plurality of DQ buffers arranged in correspondence with the DQ decoders to receive data on DQ lines selected by the DQ decoders for each I/O,
a spare DQ line commonly used by the DQ lines belonging to respective I/Os,
a spare sense amplifier circuit which receives data read out from a spare memory cell,
a spare column switch for selecting connection of the spare sense amplifier circuit to the spare DQ line,
first storage means for storing an address of a DQ line in which a failure has occurred, and
second storage means, arranged for each I/O, for storing an I/O to which the failure-DQ line belongs,
wherein, when the address stored in the first storage means is accessed, the DQ line belonging to the I/O stored in the second storage means and having the address stored in the first storage means, a sense amplifier circuit connected to the DQ
line, and a column switch selecting the sense amplifier circuit are respectively replaced with the spare DQ line, the spare sense amplifier circuit, and the spare column switch, and the spare DQ line, the spare sense amplifier circuit, and the spare
column switch are commonly used by the DQ lines belonging to respective I/Os.
According to the second aspect of the present invention, in the semiconductor memory device according to the first aspect, the first storage means comprises a fuse circuit for storing information on the number of bits corresponding to the number
of DQ lines belonging to each I/O.
According to the third aspect of the present invention, in the semiconductor memory device according to the first aspect, the second storage means comprises a fuse circuit for storing 1-bit information.
According to the fourth aspect of the present invention, there is provided a semiconductor memory device comprising
a plurality of memory cell arrays in which memory cells are laid out in a matrix form,
row decoders arranged in correspondence with the plurality of memory cell arrays to select a row of each of the memory cell arrays on the basis of a row address signal,
sense amplifier circuits arranged in correspondence with the plurality of memory cell arrays to receive data read out from memory cells on the row selected by the row decoders,
DQ lines which are arranged in correspondence with the sense amplifier circuits, and commonly used in the plurality of memory cell arrays,
column switches arranged in correspondence with the sense amplifier circuits to select sense amplifier circuits to be connected to the DQ lines on the basis of a column address signal,
a plurality of DQ decoders for performing a selection operation for the DQ lines on the basis of the column address signal for each I/O,
a plurality of DQ buffers arranged in correspondence with the DQ decoders to receive data on DQ lines selected by the DQ decoders for each I/O,
a spare DQ line commonly used by the DQ lines belonging to respective I/Os,
a spare sense amplifier circuit which receives data read out from a spare memory cell,
a spare column switch for selecting connection of the spare sense amplifier circuit to the spare DQ line,
first storage means for storing an address of a DQ line in which a failure has occurred,
second storage means, arranged for each I/O, for storing an I/O to which the failure-DQ line belongs, and
switching means for switching a data path extending to a DQ buffer corresponding to the failure-DQ line from the failure-DQ line belonging to the I/O stored in the second storage means and having the address stored in the first storage means, to
a data path extending from the spare DQ line to the DQ buffer corresponding to the failure-DQ line when the address stored in the first storage means is accessed.
According to the fifth aspect of the present invention, in the semiconductor memory device according to the fourth aspect, the first storage means comprises a fuse circuit for storing information on the number of bits corresponding to the number
of DQ lines belonging to each I/O.
According to the sixth aspect of the present invention, in the semiconductor memory device according to the fourth aspect, the second storage means comprises a fuse circuit for storing 1-bit information.
According to the seventh aspect of the present invention, there is provided a semiconductor memory device comprising
a plurality of memory cell arrays in which memory cells are laid out in a matrix form,
row decoders arranged in correspondence with the plurality of memory cell arrays to select a row of each of the memory cell arrays on the basis of a row address signal,
sense amplifier circuits arranged in correspondence with the plurality of memory cell arrays to receive data read out from memory cells on the row selected by the row decoders,
DQ lines which are arranged in correspondence with the sense amplifier circuits, and commonly used in the plurality of memory cell arrays,
column switches arranged in correspondence with the sense amplifier circuits to select sense amplifier circuits to be connected to the DQ lines on the basis of a column address signal,
a plurality of DQ decoders for performing a selection operation for the DQ lines on the basis of the column address signal for each I/O,
a plurality of DQ buffers arranged in correspondence with the DQ decoders to receive data on DQ lines selected by the DQ decoders for each I/O,
a spare DQ line commonly used by the DQ lines belonging to respective I/Os,
a plurality of spare sense amplifier circuits which receive data read out from a spare memory cell,
a spare column switch for selecting connection of the plurality of spare sense amplifier circuits to the spare DQ line,
first detection means, arranged in correspondence with the plurality of spare sense amplifier circuits, for storing an address of a DQ line in which a failure has occurred, and detecting access to the stored address,
second detection means for storing, for each I/O, information on whether a DQ line having the accessed address must be replaced, and when the first detection means detects the access to the address, detecting, for each I/O, the DQ line having the
accessed address which must be replaced on the basis of the information, and
switching means for switching a data path extending to a DQ buffer corresponding to the DQ line which must be replaced from the DQ line which must be replaced and detected by the second detection means, to a data path extending from the spare DQ
line to the DQ buffer corresponding to the DQ line which must be replaced for each of the spare sense amplifier circuits when the second detection means detects that the DQ line must be replaced.
According to the eighth aspect of the present invention, in the semiconductor memory device according to the seventh aspect, the first detection means comprises a fuse circuit for storing information on the number of bits corresponding to the
number of DQ lines belonging to each I/O.
According to the ninth aspect of the present invention, in the semiconductor memory device according to the seventh aspect, the second detection means comprises a fuse circuit for storing information on the number of bits corresponding to the
plurality of spare sense amplifier circuits.
According to the 10th aspect of the present invention, there is provided a semiconductor memory device comprising
a plurality of memory cell arrays in which memory cells are laid out in a matrix form,
row decoders arranged in correspondence with the plurality of memory cell arrays to select a row of each of the memory cell arrays on the basis of a row address signal,
sense amplifier circuits arranged in correspondence with the plurality of memory cell arrays to receive data read out from memory cells on the row selected by the row decoders,
DQ lines which are arranged in correspondence with the sense amplifier circuits, and commonly used in the plurality of memory cell arrays,
column switches arranged in correspondence with the sense amplifier circuits to select sense amplifier circuits to be connected to the DQ lines on the basis of a column address signal,
a plurality of DQ decoders for performing a selection operation for the DQ lines on the basis of the column address signal for each I/O,
a plurality of DQ buffers arranged in correspondence with the DQ decoders to receive data on DQ lines selected by the DQ decoders for each I/O,
a spare DQ line commonly used by the DQ lines belonging to respective I/Os,
a plurality of spare sense amplifier circuits which receive data read out from a spare memory cell,
a spare column switch for selecting connection of the plurality of spare sense amplifier circuits to the spare DQ line,
first detection means, arranged in correspondence with the plurality of spare sense amplifier circuits, for storing an address of a DQ line in which a failure has occurred, and detecting access to the stored address,
second detection means for storing, for each I/O, information on whether a DQ line having the accessed address must be replaced, and when the first detection means detects the access to the address, detecting, for each I/O, the DQ line having the
accessed address which must be replaced on the basis of the information,
third detection means for detecting access to a memory cell array to be replaced, and
switching means for switching a data path extending to a DQ buffer corresponding to the DQ line detected by the second detection means from the DQ line of the memory cell array to be replaced that is detected by the second detection means, to a
data path extending from the spare DQ line to the DQ buffer corresponding to the DQ line which must be replaced for each of the spare sense amplifier circuits when the second detection means detects the DQ line, and the third detection means detects the
access.
According to the 11th aspect of the present invention, in the semiconductor memory device according to the 10th aspect, the first detection means comprises a fuse circuit for storing information on the number of bits corresponding to the number
of DQ lines belonging to each I/O.
According to the 12th aspect of the present invention, in the semiconductor memory device according to the 10th aspect, the second detection means comprises a fuse circuit for storing information on the number of bits corresponding to the
plurality of spare sense amplifier circuits.
According to the 13th aspect of the present invention, in the semiconductor memory device according to the 10th aspect, the third detection means comprises a fuse circuit storing information on the number of bits corresponding to the number of
memory cell arrays independently activated.
According to the 14th aspect of the present invention, there is provided a redundancy system comprising
a memory in which address spaces of bits to be simultaneously transferred are the same,
an address fuse box in which an address subjected to redundancy is programmed,
determination means for determining whether the address programmed in the address fuse box coincides with an accessed address with respect to the memory,
a fuse circuit for storing an I/O at which the address programmed in the address fuse box is used, and
switching means for switching a data path having the address programmed in the fuse circuit at the I/O stored in the fuse circuit to another data path when the determination means determines that the programmed address coincides with the accessed
address.
According to the 15th aspect of the present invention, there is provided an address identification system comprising
a data access system having a plurality of parallel data layers for a single address,
a group of fuse boxes for storing a failure-address,
a coordinate system for designating the fuse boxes, and
a group of identification fuse bits which are arranged for respective input/output paths of data output parallel to the single address of the data access system, and in which a coordinate of a fuse box used for each input/output path
corresponding to a data layer of the data access system is programmed,
wherein a data layer having the address stored in the fuse box is identified for an input address.
According to the 16th aspect of the present invention, there is provided an address identification method in an address identification system,
the address identification system comprising
a data access system having a plurality of parallel data layers for a single address,
a group of fuse boxes for storing a failure-address,
a coordinate system for designating the fuse boxes, and
a group of identification fuse bits which are arranged for respective input/output paths of data output parallel to the single address of the data access system, and in which a coordinate of a fuse box used for each input/output path
corresponding to a data layer of the data access system is programmed,
the address identification method in the address identification system, comprising the steps of
programming the coordinate of the fuse box used for each input/output path corresponding to the data layer of the data access system in an identification fuse bit, and
identifying a data layer having the address stored in the fuse box for an input address.
According to the 17th aspect of the present invention, in the address identification method of the address identification system according to the 16th aspect, the fuse box has a plurality of fuse bits corresponding to bits of an address, and the
fuse bits are programmed to selectively respond to an address.
According to the 18th aspect of the present invention, in the address identification method of the address identification system according to the 16th aspect, the coordinate system for designating the fuse boxes comprises a plurality of bit
groups constituted by a plurality of bits, one fuse box is designated by designating one bit in each of the bit groups, and all fuse boxes are designated by a combination of bits each from each bit group.
According to the 19th aspect of the present invention, in the address identification method of the address identification system according to the 16th aspect, the group of identification fuse bits expressing the coordinate system that are
arranged for the respective input/output paths of data output parallel has fuse bits corresponding to bits of a plurality of bit groups constituted by a plurality of bits.
According to the 20th aspect of the present invention, in the address identification method of the address identification system according to the 16th aspect, a bit corresponding to the coordinates of the fuse box used for each input/output path
corresponding to the data layer is programmed on the identification fuse bits, and a data layer which responds to the fuse box for an address is identified.
According to the 21st aspect of the present invention, there is provided a memory system comprising
a memory chip,
a CPU for controlling read/write of data from/in the memory chip, and
a bus for exchanging data between the memory chip and the CPU,
wherein the memory chip comprises
a memory cell array,
a spare memory cell,
fuse means for, when a failure occurs in a memory cell of the memory cell array, replacing the failure-memory cell with the spare memory cell,
read/write means for reading/writing data from/in the memory cell array in response to an address and a command supplied from the CPU,
input means for supplying data from the CPU via the bus to the read/write means,
output means for supplying data read out from the memory cell array by the read/write means to the CPU via the bus,
internal clock generation means for generating an internal clock from an external clock supplied from the CPU, and controlling the read/write means, the input means, and the output means on the basis of the internal clock, and
fuse program means for programming a failure-address in the fuse means on the basis of a fuse program signal supplied from the CPU,
whereby, after the CPU writes data in a memory cell of the memory cell array, the data is read out and subjected to verification, in the case of incoincidence, the CPU supplies the fuse program signal to the fuse program means, the fuse program
means programs the failure-address in the fuse means, and a memory cell in which a failure has occurred is replaced with the spare memory cell on the basis of the address programmed in the fuse means.
According to the 22nd aspect, in the memory system according to the 21st aspect, the internal clock generation means comprises
a clock buffer for generating the internal clock on the basis of the external clock supplied from the CPU, and supplying the internal clock to the read/write circuit, and
a synchronous circuit for eliminating a skew of the internal clock output from the clock buffer with respect to the external clock, and outputting the internal clock from which the skew is eliminated to the input means and the output means.
According to the 23rd aspect of the present invention, there is provided a redundancy method in a memory system,
wherein the memory system comprises
a memory chip,
a CPU for controlling read/write of data from/in the memory chip, and
a bus for exchanging data between the memory chip and the CPU,
wherein the memory chip comprises
a memory cell array,
a spare memory cell,
fuse means for, when a failure occurs in a memory cell of the memory cell array, replacing the failure-memory cell with the spare memory cell,
read/write means for reading/writing data from/in the memory cell array in response to an address and a command supplied from the CPU,
input means for supplying data from the CPU via the bus to the read/write means,
output means for supplying data read out from the memory cell array by the read/write means to the CPU via the bus,
internal clock generation means for generating an internal clock from an external clock supplied from the CPU, and controlling the read/write means, the input means, and the output means on the basis of the internal clock, and
fuse program means for programming a failure-address in the fuse means on the basis of a fuse program signal supplied from the CPU,
the redundancy method in the memory system, comprising
the first step of writing data from the CPU via the bus in the memory chip,
the second step of reading out the written data from the memory chip to the CPU via the bus,
the third step of causing the CPU to verify the data written in the memory chip in the first step with the data read out from the memory chip in the second step, and
the fourth step of, when incoincidence between the two data is detected in the third step, supplying the fuse program signal from the CPU to the fuse program means, and programming a failure-address in the fuse means.
According to the 24th aspect of the present invention, in the redundancy method of the memory system according to the 23rd aspect, the first to fourth steps are repeatedly executed for each memory cell in the memory cell array.
According to the 25th aspect of the present invention, the redundancy method of the memory system according to the 23rd aspect further comprises between the third and fourth steps
the fifth step of checking the number of usable fuse means,
wherein, in the fifth step, if that usable fuse means is left is detected, the fourth step is executed to program the failure-address in the fuse means, and if that no usable fuse means is left is detected, a system failure is determined to stop
redundancy.
According to the 26th aspect of the present invention, the redundancy method of the memory system according to the 23rd aspect further comprises between the third and fourth steps
the fifth step of checking the number of usable fuse means,
wherein, in the fifth step, if that usable fuse means is left is detected, the fourth step is executed to program the failure-address in the fuse means, and if that no usable fuse means is left is detected, a system failure is determined to stop
redundancy.
The functions of these aspects will be described below.
According to the first to sixth aspects, since only a memory cell belonging to one I/O where a failure has occurred is replaced, the memory cell can be efficiently remedied for a larger number of bits. The spare DQ line is common t o the
respective I/Os, and need not be arranged for each I/O. Only a 1-bit fuse circuit representing whether the spare DQ line is used is arranged, contributing to high integration of the semiconductor memory device.
According to the seventh to ninth aspects, since spare replacement for sense amplifiers in sense amplifier circuits belonging to different I/Os can be independently performed by each spare sense amplifier in the spare sense amplifier circuit,
more efficient remedy can be performed even for a larger number of bits. The spare DQ line is common to the respective I/Os, and need not be arranged for each I/O, contributing to high integration of the semiconductor memory device.
According to the 10th to 13th aspects, spare replacement for sense amplifiers in sense amplifier circuits belonging to different I/Os can be independently performed by each spare sense amplifier in the spare sense amplifier circuit in units of
memory cell arrays independently activated. Therefore, more efficient remedy can be performed even for a larger number of bits.
The spare DQ line is common to the respective I/Os, and need not be arranged for each I/O, contributing to high integration of the semiconductor memory device. In addition, since the data transfer path extending from the spare DQ buffer is used
as the data transfer path extending from the DQ buffer, the capacity of the spare DQ line can be set substantially equal to that of another DQ line to make the data transfer speed constant.
According to the 14th aspect, the fuse circuit can have information on I/Os which cannot be identified by only an address supplied to the system in a memory wherein the address spaces of bits simultaneously transferred are the same. Accordingly,
the redundancy system capable of efficiently remedying a failure even for a larger number of bits can be provided.
According to the 15th aspect, by arranging the identification fuse bits in which the coordinates of a fuse box used for each I/O corresponding to the data layer of the system are programmed in a multi-bit memory or the like, the address
identification system capable of identifying the same addresses of I/Os, and efficiently performing spare replacement can be provided.
According to the 16th aspect, in a multi-bit memory or the like, the coordinates of the fuse box used for each I/O corresponding to the data layer of the system are programmed in the identification fuse bits, and the data layer of the address
stored in the fuse box is identified for an input address. Therefore, the address identification method capable of efficiently performing spare replacement can be provided.
According to the 17th aspect, the fuse box is constituted by a plurality of fuse bits corresponding to the bits of an address, and the fuse bits are programmed to selectively respond to the address.
According to the 18th aspect, the coordinate system for designating the fuse box consists of a plurality of bit groups constituted by a plurality of bits. One fuse box can be designated by designating one bit in each bit group, and all fuse
boxes can be designated by a combination of bits each from each bit group.
According to the 19th aspect, the group of identification fuse bits for expressing the coordinate system that are respectively arranged for the input/output paths of data output parallel can be constituted by fuse bits corresponding to the bits
of a plurality of bit groups formed of a plurality of bits.
According to the 20th aspect, when bits corresponding to the coordinate of the fuse box used for each input/output path corresponding to the data layer are programmed on the identification fuse bits, a data layer which responds to the fuse box
for an address can be identified.
According to the 21st and 22nd aspects, when a failure occurs in a memory cell due to a deterioration over time or the like upon incorporating the memory cell into the memory system, after test data from the CPU is written, the data is read out
and verified. The spare memory cell can replace and remedy the failure-memory cell.
According to the 23rd aspect, when a failure occurs in a memory cell due to a deterioration over time or the like upon incorporating the memory cell into the memory system, after test data from the CPU is written, the data is read out and
verified. The spare memory cell can replace and remedy the failure-memory cell.
According to the 24th aspect, in the redundancy method of the 23rd aspect, if the first to fourth steps are repeatedly executed for each memory cell in the memory cell array, all the memory cells in the memory cell array can be verified.
According to the 25th and 26th aspects, in the redundancy method of the 23rd aspect, when verification is performed while checking the number of usable fuse means, an unnecessary test with respect to a memory chip which cannot be remedied can be
avoided.
Additional object and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The object and advantages of the invention
may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of
the preferred embodiments given below, serve to explain the principles of the invention.
FIG. 1 is a block diagram showing a conventional multi-bit memory;
FIG. 2 is a circuit diagram schematically showing an example of how to take column redundancy in the multi-bit memory;
FIG. 3 is a circuit diagram showing only an extracted portion related to decoding by a column address signal in a multi-bit memory in order to explain a semiconductor memory device according to the first embodiment of the present invention;
FIG. 4 is a circuit diagram showing a fuse box in the circuit shown in FIG. 3;
FIG. 5 is a circuit diagram showing a fuse circuit in the circuit shown in FIG. 3;
FIG. 6 is a circuit diagram showing a data path switching circuit for switching the data path extending from a failure-DQ line to a DQ buffer, to the data path extending from a s pare memory cell to the DQ buffer upon performing redundancy in the
circuit shown in FIG. 3;
FIG. 7 is a circuit diagram schematically showing only an extracted portion related to decoding by a column address signal in a multi-bit memory in order to explain a semiconductor memory device according to the second embodiment of the present
invention;
FIG. 8 is a circuit diagram showing an example of the arrangement of a fuse box for selecting a sense amplifier in a sense amplifier circuit belonging to each I/O in the circuit shown in FIG. 7;
FIG. 9 is a circuit diagram showing an example of the arrangement of a fuse box representing an I/O at which a specific sense amplifier in a spare sense amplifier circuit in the circuit shown in FIG. 7 is used;
FIG. 10 is a circuit diagram showing a simplified data path switching circuit for switching the data path extending from a failure-DQ line to a DQ buffer, to the data path extending from a spare memory cell to the DQ buffer upon performing
redundancy in the circuit shown in FIG. 7;
FIG. 11 is a circuit diagram schematically showing only an extracted portion related to decoding by a column address signal in a multi-bit memory in order to explain a semiconductor memory device according to the third embodiment of the present
invention;
FIG. 12 is a circuit diagram showing a fuse box for selecting a sense amplifier in a sense amplifier circuit belonging to each I/O for each memory cell array which can be independently activated in the circuit shown in FIG. 11;
FIG. 13 is a circuit diagram showing a fuse box representing an I/O at which a specific sense amplifier in a spare sense amplifier is used, a fuse box representing an I/O at which the spare is used when a memory cell array is selected, and a
circuit portion related to them in the circuit shown in FIG. 11;
FIG. 14 is a circuit diagram showing a data path switching circuit in FIG. 11;
FIG. 15 is a view showing the address space representing the group of memory cells or data to be entirely replaced with a spare at once in an actual memory in order to explain a redundancy system and method and an address identification system
and method according to the fourth embodiment of the present invention;
FIG. 16 is a view for explaining the function of an address fuse box;
FIG. 17 is a view showing the fuse box space constituted by 352 fuse boxes;
FIG. 18A is an explanatory view of the fixed vector of the identification space corresponding to FIG. 17;
FIG. 18B is an explanatory view of the fixed vector of the identification space corresponding to FIG. 17;
FIG. 19 is a block diagram showing a memory system according to the fifth embodiment of the present invention; and
FIG. 20 is a flow chart for explaining the redundancy method in the memory system shown in FIG. 19.
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below with reference to the several views of the accompanying drawing.
FIG. 3 is a circuit diagram for explaining the redundancy system and method of a semiconductor memory device according to the first embodiment of the present invention, and schematically shows only an extracted portion related to decoding by a
column address signal in the multi-bit memory shown in FIG. 1.
More specifically, the circuit shown in FIG. 3 is different from the conventional circuit shown in FIG. 2 in that spare DQ lines 15c to be replaced are arranged for a plurality of I/Os instead of arranging the spare DQ lines 15b for each I/O.
The spare DQ lines 15c are connected to a spare sense amplifier circuit 13c and a spare memory cell (not shown) via a spare column switch 14c. Eight pairs of DQ lines 15a except for the spare DQ lines 15b in FIG. 2 belong to each I/O.
The spare DQ lines 15c are common to respective I/Os, and are commonly connected to all DQ decoders 16-1, 16-2, . . . For both the spare DQ line 15c and the regular DQ line 15a, a sense amplifier circuit to be connected to the DQ line is
selected by a column switch 14a or 14c selected by a column address signal.
A fuse box 20 belongs to one I/O, and is constituted by 3-bit fuse circuits 20a, 20b, and 20c for identifying which of the eight pairs of DQ lines 15a selected by a column address signal are failure-DQ lines.
A 1-bit fuse circuit 21-1, 21-2, . . . arranged for each I/O is used to designate whether the spare DQ lines 15c are used.
FIG. 4 shows an example of the arrangement of the fuse box 20 in the circuit shown in FIG. 3. Each of the fuse ci | | |
