Method and apparatus for determining a critical dwell time for use in motor controls

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STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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BACKGROUND OF THE INVENTION

The present invention relates to motor controllers and more particularly, to a method and an apparatus for altering stator winding voltages to eliminate greater than twice over voltage.

Many motor applications require that a motor be driven at various speeds. Motor speed can be adjusted with an Adjustable Speed Drive (ASD) which is placed between a voltage source and an associated motor that can excite the motor at various frequencies. One commonly used type of ASD uses a three-phase Pulse Width Modulated (PWM) inverter and associated PWM controller which can control both voltage and frequency of signals that eventually reach motor stator windings.

A three-phase PWM controller receives three reference or modulating signals and a triangle carrier signal, compares each modulating signal to the carrier signal and generates firing signals consisting of a plurality of pulses corresponding to each modulating signal. When a modulating signal has a greater instantaneous amplitude than the carrier signal, a corresponding firing signal is high producing a pulse on-time. When a modulating signal has an instantaneous amplitude that is less than the carrier signal, a corresponding firing signal is low producing a pulse off-time.

The firing signals are used to control the PWM inverter. A three-phase PWM inverter consists of three pairs of switches, each switch pair including series arranged upper and lower switches configured between positive and negative DC power supplies. Each pair of switches is linked to a unique motor terminal by a unique supply line, each supply line is connected to a node between an associated pair of switches. Each firing signal controls an associated switch pair to alternately connect a stator winding between the positive and negative DC power supplies to produce a series of high frequency voltage pulses that resemble the firing signals. A changing average of the high frequency voltage pulses over a period defines a fundamental low frequency alternating line-to-line voltage between motor terminals that drives the motor.

Insulated Gate Bipolar Transistors (IGBTs) are the latest power semiconductor switches used in the PWM inverter, IGBTs have fast rise times and associated switching speeds (e.g. 50-400 ns) that are at least an order of magnitude faster than BJTs and other similar devices. At IGBT switching speeds, switching frequency and efficiency, and the quality of terminal voltages, are all appreciably improved. In addition, the faster switching speeds reduce harmonic heating of the motor winding as well as reduce audible motor lamination noise.

While IGBT PWMs are advantageous for all of the reasons identified above, when combined with certain switch modulating techniques (i.e. certain on/off switching sequences), IGBT fast dv/dt or rise times can reduce the useful life of motor components and/or drive to motor voltage supply lines. In particular, while most motors and supply lines are designed to withstand operation at rated line voltages for long periods and to withstand predictable overvoltage levels for short periods, in many cases, fast switch rise times causes overvoltages that exceed design levels.

For a long time the industry has recognized and configured control systems to deal with twice overvoltage (i.e. twice the PWM inverter DC power supply level) problems. As well known in the controls art, twice overvoltage levels are caused by various combinations of line voltage rise time and magnitude, imperfect matches between line-to-line supply cable and motor surge impedances, and cable length. Line voltage frequency and switch modulating techniques have little effect on twice overvoltage levels.

One common way to cope with twice overvoltage levels has been to reduce reflected voltage by terminating the cable supply lines at the motor terminals with a cable to motor surge impedance matching network. Resistor-Inductor-Capacitor or R-L-C filter networks mounted at the drive output are also used to change and reduce the slope of the voltage pulses (i.e. the turn on times) as they arrive. This network increases the cable distance where twice voltage in the motor terminals is developed to a length outside the application distance of interest. In addition, to reduce the possibility of damage from periodic twice overvoltage levels, most cable supply lines and motors are insulated to withstand periodic twice overvoltage levels. Thus, the industry has developed different system configurations for dealing with twice overvoltage.

Unfortunately, there is another potentially more damaging overvoltage problem that has not been satisfactorily dealt with. The second overvoltage problem is referred to herein as greater than twice overvoltage. Unlike twice overvoltage, greater than twice overvoltage is caused by faster IGBT switching frequencies and faster IGBT dv/dt rise times interacting with two different common switch modulating techniques, that result in overvoltage problems referred to as "double pulsing" and "polarity reversal".

Referring to FIG. 1, double pulsing will be described in the context of an IGBT inverter generated line-to-line voltage V.sub.i applied to a line cable and a resulting motor line-to-line terminal voltage V.sub.m. Initially, at time .tau..sub.1, the line is shown in a fully-charged condition (V.sub.i (.tau..sub.1)=V.sub.m (.tau..sub.1)=V.sub.DC). A transient motor voltage disturbance is initiated in FIG. 1 by discharging the line at the inverter output to zero voltage, starting at time .tau..sub.2, for approximately 4 .mu.sec. The pulse propagation delay between the inverter terminals and motor terminals is proportional to cable length and is approximately 1 .mu.sec for the assumed conditions. At time .tau..sub.3, 1 .mu.sec after time .tau..sub.2, a negative going V.sub.DC voltage has propagated to the motor terminals. In this example, a motor terminal reflection coefficient .GAMMA..sub.m is nearly unity. Thus, the motor reflects the incoming negative voltage and forces the terminal voltage V.sub.m to approximately negative bus voltage:

A reflected wave (-V.sub.DC) travels from the motor to the inverter in 1 .mu.sec and is immediately reflected back toward the motor. Where an inverter reflection coefficient .GAMMA..sub.i is approximately negative unity, a positive V.sub.DC pulse is reflected back toward the motor at time .tau..sub.4. Therefore, at time .tau..sub.4 the discharge at time .tau..sub.2 alone causes a voltage at the motor terminal such that:

In addition, at time .tau..sub.4, with the motor potential approaching V.sub.DC due to the .tau..sub.2 discharge, the inverter pulse V.sub.i (.tau..sub.4) arrives and itself recharges the motor terminal voltage to V.sub.DC. Pulse V.sub.i (.tau..sub.4) is reflected by the motor and combines with V.sub.m (.tau..sub.4) to achieve a peak value of approximately three times the DC rail value:

Referring to FIG. 2 polarity reversal will be described in the context of an IGBT inverter generated line-to-line voltage V.sub.il and a resulting motor line-to-line voltage V.sub.ml. Polarity reversal occurs when the firing signal of one supply line is transitioning into overmodulation while the firing signal of another supply line is simultaneously transitioning out of overmodulation. Overmodulation occurs when a reference signal magnitude is greater than the maximum carrier signal magnitude so that the on-time or off-time of a switch is equal to the duration of the carrier period. Polarity reversal is common in all types of PWM inverter control.

Initially, the inverter line-to-line voltage V.sub.il (.tau..sub.5) is zero volts. At time .tau..sub.6, the inverter voltage V.sub.il (.tau..sub.6) is increased to V.sub.DC and, after a short propacation period, a V.sub.DC pulse is received and reflected at the motor terminals thus generating a 2 V.sub.DC pulse across associated motor lines. At time .tau..sub.7, the line-to-line voltage switches polarity (hence the term polarity reversal) so that the inverter voltage V.sub.il (.tau..sub.7) is equal to -V.sub.DC when the line-to-line motor voltage V.sub.ml (.tau..sub.7) has not yet dampened out to a DC value (i.e. may in fact be 2 V.sub.DC). After a short propagation period, the -V.sub.DC inverter pulse reaches the motor, reflects, and combines with the inverter reflected pulse -V.sub.DC and the positive voltage 2 V.sub.DC on the motor. The combination generates an approximately -3 V.sub.DC line-to-line motor voltage V.sub.ml (.tau..sub.8) at time .tau..sub.8.

In reality, the amplitude of overvoltages will often be less than described above due to a number of system variables including line AC resistance damping characteristics, DC power supply level, pulse dwell time, carrier frequency f.sub.c modulation techniques, and less than unity reflection coefficients (.GAMMA..sub.m).

One solution to the double pulsing problem has been to increase the zero voltage dwell time between line-to-line inverter pulses. In other words, referring again to FIG. 1, the discharge time between pulses would be extended from the present 4 .mu.secs so that, prior to the second pulse V.sub.i (.tau..sub.4) reaching the motor terminals, the motor terminal voltage transient V.sub.m reaches a steady state DC value.

While increasing the zero voltage dwell time between line-to-line inverter pulses eliminates greater than twice overvoltage due to double pulsing, this solution can disadvantageously reduce the amplitude of the resulting fundamental low frequency terminal voltage where high carrier frequencies and overmodulation occurs. For example, referring to FIG. 3, a series of high frequency voltage pulses 5 at a motor terminal and a resulting fundamental low frequency terminal voltage 6 can be observed. In FIG. 3, a positive phase of the low frequency voltage begins at .tau..sub.9 and ends at .tau..sub.10.

To eliminate greater than twice over voltage, one pulse limiting scheme indiscriminately increases the duration of each off time period that is less than a minimum allowable off time. In FIG. 3, the off times of pulses during the overmodulation period i.e., is .zeta..sub.2 and .zeta..sub.3) are less than the minimum allowable off time and therefore result in on times greater than the maximum on time and thus would be limited. In addition, in many cases greater than twice over voltage will occur prior to and just after overmodulation. Thus, re:erring still to FIG. 3, during periods just before period .zeta..sub.2 and just after period .zeta..sub.3 off times will also often. be limited. Where the magnitude of the DC power supply is reduced substantially, the number of overmodulation carrier periods having limited on-times increase, proportionally until, at some point, the reduced on-time noticeably affects the low frequency terminal voltage magnitude. In other words, maximum power output is substantially reduced through blind limitation of firing pulses during overmodulation.

While FIG. 3 is only exemplary, it can be seen that during the positive phase (i.e. .tau..sub.9 -.tau..sub.10), the four firing pulses that would normally occur during carrier periods .zeta..sub.1 -.zeta..sub.4 would likley all be limited to a maximum on-time according to prior art methods of reducing greater than twice overvoltage. In addition, pulses during periods just before period .zeta..sub.1 and just after period .zeta..sub.4 may also be limited. In many cases, especially where the DC supply magnitude is minimal or reduced, the reduction in low frequency terminal voltage is unacceptable.

In addition to reducing the magnitude of the fundamental low frequency voltage 6, this solution does not address the polarity reversal problem.

Another solution to the greater than twice overvoltage problem is described in U.S. Pat. No. 5,671,130 entitled METHOD AND APPARATUS FOR CONTROLLING VOLTAGE REFLECTIONS USING A MOTOR CONTROLLER which was filed on Aug. 23, 1996 and is commonly owned with this application. According to this solution a motor controller modifies firing pulses that are provided to an inverter in a manner calculated to eliminate greater than twice overvoltage switching sequences. When the period between two voltage changes is less than the period required for a substantially steady state voltage near zero to be reached, the period between the two changes is increased. Where overmodulation switching sequences result in greater than twice overvoltage due to polarity reversal, the overmodulation switching sequence is altered to eliminate the possibility of greater than twice overvoltage.

This solution contemplates two different methods of altering the switching sequence referred to as the Maximum-Minimum Pulse Technique (MMPT) and the Pulse Elimination Technique (PET) methods. According to the MMPT method, when a PWM pulse has characteristics which could generate greater than twice overvoltage, the pulse width is altered so that its duration is set equal to or between the minimum and maximum pulse times allowed. Importantly, only pulses after importantly, only pulses that cross the threshold level for double pulsing induced motor voltages greater than twice overvoltage and during polarity reversal periods are altered so that the resulting terminal voltage magnitude is only minimally effected. Nevertheless, the terminal voltage magnitude is noticeably reduced as some positive pulse durations during positive half cycles and some negative pulse durations during negative half cycles are reduced when the MMPT method is employed.

According to the PET method, instead of only limiting pulses to within the maximum and minimum pulse times, some of the pulses having characteristics which could generate greater than twice overvoltage are eliminated. In other words, some of the positive pulse durations during positive half cycles are increased and set equal to the carrier period and some of the negative pulse durations are increased and set equal to the carrier period which tend to offset the reduced pulse durations. The result is a terminal voltage magnitude which is essentially unaffected by pulse alterations.

While this solution effectively eliminates greater than twice overvoltage while maintaining a desired terminal voltage, this solution requires a relatively large amount of signal monitoring and comparing to determine which PWM pulses are likely to generate greater than twice overvoltage. For this reason, it may be difficult to implement this solution using the simple microprocessors which are provided in many motor controllers.

In addition, while the critical dwell time between consecutive firing pulses can be determined through experimentation as described in the above reference, this process is somewhat cumbersome and time consuming.

Therefore, it would be advantageous to have a method and apparatus that could eliminate greater than twice overvoltage without distorting the fundamental components of motor terminal voltages and which is relatively simple to implement. In addition, it would be advantageous to have a method and an apparatus for automatically determining the critical dwell time required to eliminate greater than twice overvoltage as a function of the type of cable used for supply lines.

BRIEF SUMMARY OF THE INVENTION

The present invention modifies reference or modulating signals that are provided to a PWM controller for comparison to a carrier signal for generating PWM firing signals to drive a PWM inverter in a manner calculated to eliminate greater than twice overvoltage switching sequences. PWM signal durations, which can be used to determine if greater than twice overvoltage is likely, are directly related to the modulating signal. Therefore, PWM pulse characteristics (i.e. pulse durations) which are likely to cause greater than twice overvoltage are reflected in the modulating signal and the modulating signal can be used to determine during which carrier periods the PWM signals will likely cause greater than twice overvoltage.

In addition, because the modulating signal and PWM pulse durations are directly related, the modulating signal can be controlled or modified to control PWM pulse durations and thereby eliminate greater than twice overvoltage. To this end, according to the present invention, modulating signal characteristics which are known to cause greater than twice overvoltage are identified. Then, during controller operation, the modulating signal is monitored and, when modulating signal characteristics match the characteristics known to cause greater than twice overvoltage, the modulating signal is altered so that greater than twice overvoltage is not generated.

One object of the invention is to eliminate greater than twice overvoltage. By identifying modulating signal characteristics which generate greater than twice overvoltage, comparing modulating signals during controller operation to the characteristics known to cause greater than twice overvoltage and modifying signals accordingly, greater than twice overvoltage can be eliminated.

Specifically, PWM pulse durations are directly related to the magnitude of the modulating signal. Therefore, a maximum voltage magnitude above which greater than twice overvoltage is known to occur can be identified. Then, during controller operation the modulating signal magnitude is monitored and compared to the maximum voltage magnitude.

When the monitored magnitude is greater than the maximum voltage magnitude an overvoltage period occurs. During an overvoltage period the modulating signal is altered by, if the modulating signal is positive, setting the modulating signal equal to a positive value which is greater than or equal to a positive peak carrier signal value and, if the modulating signal is negative, setting the modulating signal equal to a negative value which is less than or equal to a negative peak carrier signal value. Then, when the PWM controller compares the modulating signal to the carrier signal, the resulting PWM signals during overvoltage periods are tied to either the positive or negative DC bus value and switching which could cause double pulse greater than twice overvoltage is eliminated.

Thus, another object of the invention is to eliminate double pulses, resulting in greater than twice overvoltage on the motor, without requiring a large number of calculations which command excessive amounts of processor time. To this end, the only signals that must be monitored during controller operation are the modulating signals and the only calculation is to determine if a modulating signal magnitude is greater than the maximum voltage magnitude.

In another embodiment, where an overvoltage period consists of a plurality of carrier periods, for a predetermined number N of carrier periods at the beginning of the compensation period, the modulating signal is altered such that its magnitude remains at the maximum voltage magnitude. The periods during which the modulating signal remains at the maximum voltage magnitude are referred to herein as porches.

Yet another object of the invention is to eliminate greater than twice overvoltage on the motor due to polarity reversal, yet maintain a desired terminal voltage magnitude. By maintaining the maximum voltage magnitude during the porches and equating the modulating signal to an appropriate value during the remainder of the overvoltage period, the overall terminal voltage magnitude can be approximately maintained. The number of carrier periods which constitute a porch is a function of modulating signal amplitude, frequency and line characteristics and is typically on the order of 1 to 5.

In another aspect, for a predetermined number N of carrier periods at the end of an overvoltage period, the modulating signal is maintained at the maximum voltage magnitude.

Thus, one other object of the invention is to maintain the fundamental component of the terminal voltage while altering the modulating signals to eliminate greater than twice overvoltage. The modulating signal can be tracked several carrier periods in advance so that the last N carrier periods of the compensation period can be identified and altered. When a porch is added at the beginning of an overvoltage period, an identical porch is added at the end of the overvoltage period so that half-wave modulating signal symmetry is maintained which in turn maintains the fundamental terminal voltage component.

The invention also includes a method and an apparatus for determining critical dwell times between consecutive firing pulses to an inverter which will eliminate greater than twice overvoltage. To this end, the method and apparatus use supply line parameters, specifically inductance and resistance per unit length, to determine a desired critical dwell time for specific line construction. The dwell time is then used by the controller to eliminate greater than twice overvoltage.

The invention also includes a method and apparatus for, during a commissioning procedure, determining a plurality of critical dwell times corresponding to a plurality of different supply line types and storing the times as a function of line parameters in a table for use during normal motor operation. Then during normal operation, an operator uses an interface to provide line parameters which can be used to determine a correct dwell time for motor control.

Thus, another object of the invention is to facilitate easy determination of critical dwell times which are dependent on supply line parameters so that cumbersome commissioning can be avoided. To this end, a simple equation for dwell time as a function of line parameters is developed and implemented. Commissioning is further simplified by providing a lookup table of dwell times determined during the commissioning procedure.

Other and further objects, aspects and embodiments of the present invention will become apparent during the course of the following description and by reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a graph that illustrates the greater than twice overvoltage phenomenon on the motor due to the inverter modulator double pulsing problem, an inverter line-to-line voltage generated by PWM firing signals, a resulting uncompensated line-to-line motor voltage of greater than twice voltage magnitude and a compensated line-to-line motor voltage limited to twice overvoltage by the described invention;

FIG. 2 is a graph that illustrates greater than twice overvoltage phenomenon on the motor due to the inverter modulated polarity reversal problem, FIG. 2 consists of an inverter line-to-line voltage generated by the PWM modulator firing signals, a resulting uncompensated line-to-line motor voltage of greater than twice voltage magnitude and a compensated line-to-line motor voltage limited to twice overvoltage by the invention;

FIG. 3 is a graph illustrating the high frequency pulse width modulating voltage pulses and a resulting low frequency fundamental terminal voltage;

FIG. 4 is a schematic of an inventive motor controller;

FIG. 5a is a graph illustrating the line-to-ground or per phase modulating signal generator used by a PWM inverter to produce high frequency voltage pulses;

FIGS. 5b and 5c are graphs illustrating PWM firing pulses generated by comparison of the signals of FIG. 5a;

FIG. 5d is a graph illustrating a high frequency pulse generated by the firing pulses of FIGS. 5b and 5c;

FIGS. 6a and 6b are graphs illustrating firing pulses for two different motor phases;

FIG. 6c is a graph illustrating the line-to-line voltage resulting from the firing pulses shown in FIGS. 6a and 6b;

FIGS. 6d and 6e are similar to FIGS. 6a and 6b;

FIG. 6f is a graph illustrating the line-to-line voltage resulting from the firing pulses shown in FIGS. 6d and 6e;

FIG. 7 is a graph illustrating the beginning of the greater than 2 p.u. motor terminal voltage for various types of modulating signals which can be used with the present invention;

FIG. 8 is a flow chart showing a method used to determine the value of a variable N used in the methods of FIGS. 9 and 14;

FIG. 9 is a schematic of hardware according to the present invention;

FIG. 10 is a flow chart illustrating a preferred inventive method;

FIG. 11a is a graph illustrating signals used to produce firing pulses and

FIG. 11b is a graph illustrating firing pulses produced by comparing the signals of FIG. 11a;

FIG. 12a is similar to FIG. 11a except that the modulation signal has been modified according to the method of FIG. 10 and

FIG. 12b is a graph illustrating firing pulses produced by comparing the signals of FIG. 12a;

FIG. 13a is a graph illustrating an unmodified space vector modulating signal,

FIG. 13b is a graph illustrating both an unmodified modulation signal and a modulating signal modified in accordance with the method of FIG. 10,

FIG. 13c is like FIG. 13b albeit corresponding to the method of FIG. 20 and

FIG. 13d is like FIG. 13b albeit corresponding to the method of FIG. 14;

FIG. 14 is a flow chart illustrating a second preferred inventive method;

FIG. 15A is similar to FIG. 11a except that the modulation signal has been modified according to the method of FIG. 14 and FIG. 15b is a graph illustrating firing pulses produced by comparing the signals of FIG. 15a;

FIG. 16 is a graph illustrating transient charging of a drive motor cable from a single voltage pulse emitted by the drive output, twice motor terminal voltage is illustrated in this case as well as the pulse propagation time from inverter to motor t.sub.p, cable oscillation frequency ##EQU1## and transient damping time (3.tau.);

FIG. 17 shows a phase conductor cross-section area with a shaded portion denoting the effective area or skin depth used during high frequency operation;

FIG. 18 is a graph illustrating the 3.tau. cable damping time of FIG. 16 for several different cable sizes and several cable oscillation frequencies f.sub.0 ;

FIG. 19 is a table indicating critical dwell time T.alpha. for various motor HP sizes and typical cable sizes used, time T.alpha. is approximately equal to the 3.tau. damping time;

FIG. 20 is a flow chart illustrating a third preferred inventive method;

FIG. 21a is similar to FIG. 11a except that the modulation signal has been modified according to the method of FIG. 20 and

FIG. 21b is a graph illustrating firing pulses produced by comparing the signals of FIG. 21a; and

FIG. 22 is a schematic diagram of a critical dwell time identifier.

DETAILED DESCRIPTION OF THE INVENTION

A. General Overview of Solution

The present invention will be described in the context of the exemplary PWM inverter 9 shown in FIG. 4. The inverter 9 is shown connected to a PWM controller 11, a DC voltage source 18, and a motor 19. The inverter consists of six solid state switching devices 12-17 (BJT, GTO, IGBT or other transistor technology devices may be used) arranged in series pairs, each switching device 12-17 being coupled with an inverse parallel connected diode 23-29.

Each series arranged pair of switching devices 12 and 13, 14 and 15, and 16 and 17, make up a separate leg 39, 40 or 41 of the inverter 9 and have a common node which is electrically connected to a unique motor terminal 30, 31, or 32 (and thus to a unique stator winding 35, 36 or 37). Each switching device 12-17 is also electrically connected by a firing line 51-56 to controller 11 and through the controller to modulating signal modifier 7 and a modulating signal generator 20.

Source 18 is split so that it creates a high voltage rail 48 and a low voltage rail 49 and each leg 39, 40, 41 connects the high voltage rail 48 to the low voltage rail 49.

To avoid repetitive disclosure, inverter 9 and the inventive modifier 7 will be explained by referring only to leg 39 as all three legs 39, 40, and 41 of the inverter operate and are controlled in the same manner.

Generator 20, modifier 7 and controller 11 operate together to turn the switching devices 12, 13 of leg 39 on and off in a repetitive sequence that alternately connects the high and low voltage rails 48, 49 to, and produces a series of high frequency voltage pulses at, terminal 31.

Referring now to FIG. 5a, signals used by controller 11 to generate the firing pulses for leg 39 may be observed. As well known in the art, a carrier signal 67 is perfectly periodic and operates at what is known as the carrier frequency. A modulating signal 68, which is provided by the modulating signal modifier 7 and generator 20, has a much greater period than the carrier signal 67.

Referring also to FIGS. 5b and 5c an upper signal 72 and a lower signal 74 that control the upper and lower switches 12, 13, respectively, can be observed. The turn-on t.sub.on1, t.sub.on2 and turn-off t.sub.off1, t.sub.off2 times of the upper and lower signals 72, 74 come from the intersections of modulating signal 68 and carrier signal 67.

When signal 68 intersects carrier signal 67, signal 67 has a positive slope, the upper signal 72 goes off and the lower signal 74 goes on. On the other hand, when signal 68 intersects signal 67 while the carrier signal 67 has a negative slope, the upper signal 72 goes on and the lower signal 74 goes off.

Referring to FIGS. 4 and 5d, a high frequency voltage pulse 60 resulting from the upper and lower signals 72, 74 in FIGS. 5b and 5c that might be provided at terminal 31 is illustrated. When the upper signal 72 is on and the lower signal 74 is off, switching device 12 allows current to flow from the high voltage rail 48 to motor terminal 31 thus producing the positive phase 78 of pulse 60 at motor terminal 31. Ideally, when the upper signal 72 goes off and the lower signal 74 goes on, switching device 12 immediately turns off and switching device 13 immediately turns on connecting motor terminal 31 at the low voltage rail 49 producing the negative phase 80 of pulse 60 at motor terminal 31. As well known in the art, in reality, to eliminate a short between the positive and negative DC rails 48 and 49, a dead time or delay is introduced between the times when one switch turns off and an associated switch turns on. The high frequency voltage pulses average over a given period to produce a low frequency voltage at terminal 31. Ideally, the maximum amplitudes of the positive and negative phase portions 78, 80 of pulse 60 are plus or minus V.sub.DC /2.

In reality, however, at high switching frequencies associated with IGBTs and other high speed devices, voltage reflection between the motor 19 and the inverter 9 can increase the magnitude of the terminal line-to-line (30-31, 31-32, 32-30) voltage to greater than three times the DC voltage when the upper signal 72 has certain characteristics.

To substantially eliminate the greater than twice bus voltage phenomenon, modifier 7 receives a modulating signal 68 from generator 20 and determines the characteristics of the modulating signal 68, compares those characteristics to characteristics known to cause greater than twice overvoltage and, when greater than twice overvoltage is likely, alters the modulating signal 68.

Referring to FIG. 5a, carrier signal 67 can be divided into carrier periods T.sub.c wherein each carrier period T.sub.c is the time between peak carrier signal values. During any carrier period T.sub.c, the upper switch 12 will be on when the upper signal 72 is on and will be off during off periods T.sub.off on either side of the on-time T.sub.on. Near the top and bottom portions of a modulating signal 68 where the modulating signal 68 becomes substantially horizontal, the off periods T.sub.off on either side of an on-time will be approximately identical. This is particularly true where the carrier frequency is much greater than the frequency of the reference signal as is the case in motor controls or in microprocessor drives.

Thus, during any carrier period T.sub.c, when the signal generator 20 compares the carrier and modulating signals 67, 68 to generate firing signals, the resulting upper signal 72 has a characteristic on-time T.sub.on that is equal to the carrier period T.sub.c less two times an off period T.sub.off.

Referring again to FIG. 1, the double pulse problem that creates greater than twice overvoltage occurs because the discharge or off-time T.sub.off of a signal (i.e. V.sub.i from .tau..sub.2 to .tau..sub.4) is insufficiently long to allow a motor voltage V.sub.m to reach a steady state DC value before the next PWM pulse (V.sub.i) arrives at the end of the terminal. Therefore, each control system is characterized by a minimum upper switch off-time which is required to avoid double pulse greater than twice overvoltage.

Similarly, double pulse greater than twice overvoltage occurs when consecutive off-times are so large that an on time therebetween is to short to allow a motor voltage to reach a steady state DC value before the following off time. Thus, each system is also characterized by a maximum allowable upper switch off-time and an associated minimum required on time. The minimum required off-time and minimum required on time have the same duration which is referred to herein as a critical dwell time T.sub..alpha..

The present invention contemplates modifying modulating signal 68 (see FIG. 5a) in two different ways to eliminate the double pulse problem creating greater than twice overvoltage on the motor. A first way is to simply generate a modulating signal which eliminates turn-off periods and turn on periods when those periods have durations which are less than the critical dwell time T.sub..alpha.. Turn off and turn on periods are eliminated by causing the modulating signal to exceed a peak carrier value during a carrier period. To this end, when a modulating signal is positive the signal can be set equal to a positive value and, when the modulating signal is negative the modulating signal can be set equal to a negative value.

A second way to eliminate double pulse greater than twice overvoltage is to generate a modulating signal which, when compared to the carrier signal via controller 11 (see FIG. 4) generates turn on and turn off times which have durations which are greater than or equal to the critical dwell time T.sub..alpha.. By generating turn on and turn off times which are greater than or equal to time T.sub..alpha., resulting pulses allow motor voltage V.sub.m to reach a steady state prior to a change in signal V.sub.i. The critical dwell time T.sub..alpha. can be assured by maintaining the magnitude of the modulating signal within a range of .+-.V.sub.T.alpha. * where V.sub.T.alpha. * is a maximum voltage magnitude above which the turn on and turn off times are known to exceed the critical dwell time T.sub..alpha..

For example, referring still to FIG. 1, the bottom motor terminal voltage curve V.sub.m ' was generated using a modified modulating signal wherein the signal magnitude was maintained below the maximum voltage magnitude during the period illustrated such that the resulting inverter voltage V.sub.i has an extended off-time (i.e. .tau..sub.2 to .tau..sub.12) on the order of 6-7.mu.s instead of 4 .mu.s. During the extended off-time, the motor terminal voltage V.sub.m ' reaches an approximately zero steady state prior to time .tau..sub.12 and prior to the next inverter voltage pulse reaching the terminal. As a result, the overvoltage level is reduced to a maximum value of 2 V.sub.DC instead of approximately 3 V.sub.DC.

In a similar fashion, polarity reversal greater than twice overvoltage can be substantially eliminated by modifying the modulating signal to alter the duration of switch on-times. overmodulating occurs when an unmodified modulating signal amplitude exceeds the peak carrier signal value such that during one or more carrier periods the switch states in a single phase remain unchanged (i.e. do not switch). Referring to FIGS. 6a and 6b, two upper firing signals U.sub.x and U.sub.y for two different upper switches (e.g. switches 12 and 14 in FIG. 4) can be observed. Firing signal U.sub.x in FIG. 6a comes out of, and firing signal U.sub.y goes into, overmodulation at time .tau..sub.13. Therefore, in FIG. 6c, the line-to-line voltage U.sub.x -U.sub.y has a polarity reversal at time .tau..sub.13. Referring also to FIG. 2, polarity reversals like the one at time .tau..sub.13 in FIG. 6c generate greater than twice overvoltage (see time .tau..sub.8).

Referring also to FIGS. 6d and 6e, two firing signals U.sub.x ' and U.sub.y ' generated by a modulating signal modified according to the present invention can be observed. The generated firing signals U.sub.x ' and U.sub.y ' are similar to signals U.sub.x and U.sub.y except that, during a carrier period just prior to coming out of overmodulation pulse U.sub.x ' has the minimum allowable off-time (i.e. T.sub..alpha.) and, during the carrier period just after going into overmodulation signal U.sub.y ' has the minimum allowable off-time (i.e. T.sub..alpha.). Referring also to FIG. 6f, the resulting line-to-line voltage U.sub.x '-U.sub.y ' has a period between times .tau..sub.14 and .tau..sub.15 during which the line-to-line voltage can substantially reach a steady state zero level prior to swinging from the positive to the negative DC rails.

Referring again to FIG. 2, the bottom motor terminal voltage curve V.sub.ml ' is like the middle curve except that it represents line-to-line voltage where, upon going into and coming out of overmodulation, associated modulating signals are altered so that they produce firing signals like those illustrated in FIGS. 6d and 6e. As desired, the line-to-line voltage V.sub.ml ' substantially reaches a steady state zero value by time .tau..sub.16, when the line-to-line voltage is forced to the negative DC value.

To eliminate polarity reversal greater than twice overvoltage the modulating s