Method, apparatus and system for testing bumped semiconductor components

What is claimed is:

1. An interconnect for a semiconductor component comprising:

a substrate; and

a contact member configured to electrically engage a contact bump on the component, the contact member comprising a plurality of electrically conductive projections on the substrate configured to retain the contact bump therebetween, each projection comprising a raised portion of the substrate at least partially covered with a non-bonding conductive layer, each projection comprising at least one edge configured to penetrate the contact bump and at least one face configured to electrically engage the contact bump.

2. The interconnect of claim 1 wherein the substrate comprises silicon.

3. The interconnect of claim 1 wherein the contact member comprises from three to five projections.

4. The interconnect of claim 1 wherein the conductive layer comprises an element selected from the group consisting of Be, Mg, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, V, Nb, Ta, Mo, W, Tc, Re, B, C, Si and Ge.

5. An interconnect for a semiconductor component comprising:

a substrate;

a plurality of projections on the substrate sized and spaced to form a contact member configured to retain and electrically engage a contact bump on the component, the projections comprising portions of the substrate at least partially covered with an electrically conductive layer comprising a material that does not bond to the contact bump, each projection having a generally truncated pyramidal configuration comprising at least one edge configured to penetrate the contact bump and at least one face configured to electrically engage the contact bump; and

a conductor on the substrate in electrical communication with the conductive layer.

6. The interconnect of claim 5 wherein the substrate comprises silicon.

7. The interconnect of claim 5 wherein the material comprises an element selected from the group consisting of Be, Mg, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, V, Nb, Ta, Mo, W, Tc, Re, B, C, Si and Ge.

8. The interconnect of claim 5 wherein the contact member comprises from three to five projections.

9. The interconnect of claim 5 wherein the contact member comprises from three to five angled faces configured to electrically engage the contact bump.

10. An interconnect for electrically contacting a semiconductor component comprising:

a substrate; and

a contact member configured to electrically engage a contact bump on the component, the contact member comprising a plurality of projections comprising raised portions of the substrate at least partially covered with a conductive layer comprising a material that is non-bonding with the contact bump, the projections sized and spaced to retain the contact bump therebetween, the projections and the conductive layer comprising a plurality of edges configured to penetrate into the contact bump and a plurality of faces configured to electrically engage the contact bump.

11. The interconnect of claim 10 wherein the substrate comprises silicon.

12. The interconnect of claim 10 wherein the conductive layer comprises an element selected from the group consisting of Be, Mg, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, V, Nb, Ta, Mo, W, Tc, Re, B, C, Si, and Ge.

13. The interconnect of claim 10 wherein the contact member comprises from three to five projections in a spaced array.

14. An interconnect for electrically contacting a semiconductor component having contact bumps comprising:

a substrate;

a plurality of contact members on the substrate, each contact member comprising a plurality of electrically conductive projections formed in a spaced array and configured to retain and electrically engage a contact bump on the component, each projection having a truncated pyramidal configuration comprising at least one angled face configured to electrically contact the contact bump and at least one edge configured to penetrate the contact bump, such that the contact bump is penetrated by a plurality of edges and electrically contacted by a plurality of angled faces; and

at least one conductor on the substrate in electrical communication with the conductive projections.

15. The interconnect of claim 14 wherein the substrate comprises silicon and the projections comprise portions of the substrate.

16. A method for testing a semiconductor component comprising:

providing testing circuitry;

providing an interconnect for establishing electrical communication between the component and the testing circuitry, the interconnect comprising a substrate and a contact member comprising a plurality of projections comprising raised portions of the substrate at least partially covered with a non-bonding conductive layer and configured to retain and electrically contact a contact bump of the component therebetween, each projection comprising at least one edge configured to penetrate the contact bump and at least one face configured to electrically engage the contact bump;

placing the component on the interconnect with the contact bump in electrical communication with the projections, and the conductive layer in electrical communication with the testing circuitry; and

applying test signals through the contact member and the contact bump to the component.

17. The method of claim 16 wherein the conductive layer comprises an element selected from the group consisting of Be, Mg, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, V, Nb, Ta, Mo, W, Tc, Re, B, C, Si and Ge.

18. The method of claim 16 wherein each contact member comprises from three to five projections.

19. A method for testing a semiconductor component comprising:

providing testing circuitry;

providing an interconnect for establishing electrical communication between the component and the testing circuitry, the interconnect comprising a substrate and a plurality of projections comprising portions of the substrate at least partially covered with a non-bonding conductive layer and configured to retain a contact bump on the component therebetween, each projection having a generally truncated pyramidal configuration such that the projections form a contact member having a plurality of angled faces configured to electrically contact the contact bump and a plurality of edges configured to penetrate the contact bump;

placing the component on the interconnect with the contact bump in electrical communication with the conductive layer and with the testing circuitry; and

applying test signals through the conductive layer and the contact bump to the component.

20. The method of claim 19 wherein the substrate comprises silicon.

21. An interconnect for a semiconductor component comprising:

a substrate comprising silicon; and

a contact member on the substrate configured to electrically engage a contact bump on the component, the contact member comprising a plurality of projections comprising portions of the substrate configured to retain a contact bump on the component therebetween, and a conductive layer at least partially covering the projections comprising an element selected from the group consisting of Be, Mg, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, V, Nb, Ta, Mo, W, Tc, Re, B, C, Si and Ge, the projections comprising a plurality of edges for penetrating the contact bump and a plurality of angled faces for electrically contacting the contact bump.

22. The interconnect of claim 21 wherein the contact member comprises from three to five projections.

23. The interconnect of claim 21 wherein the contact member is configured to electrically engage different sizes of contact bumps on the component.

24. The interconnect of claim 21 wherein the projections comprise etched portions of the substrate.

25. The interconnect of claim 21 wherein the projections comprise generally pyramidally shaped truncated pillars.

Description Submit all comments and votes

FIELD OF THE INVENTION

This invention relates generally to semiconductor manufacture, and more particularly to an improved method, apparatus and system for testing bumped semiconductor components, such as dice and packages having contact bumps.

BACKGROUND OF THE INVENTION

One type of semiconductor die, referred to as a "bumped" die includes patterns of contact bumps formed on a face of the die. The contact bumps can be formed on wettable metal contacts on the die in electrical communication with the integrated circuits contained on the die. The contact bumps allow the die to be "flip chip" mounted to a substrate having corresponding solder wettable contacts. This mounting process was originally developed by IBM and is also known as the C4 joining process (Controlled Collapse Chip Connection).

Lead tin alloys (e.g., 95/5 lead tin alloy) and a ball limiting metallurgy (BLM) process can be used to form the bumps. Typically, the bumps are dome shaped, and have an average diameter of from 5 mils to 30 mils. Micro ball grid arrays (BGA) are formed in the smaller range, while standard ball grid arrays are formed in the larger size range. The sides of the bumps typically bow or curve outwardly from flat top surfaces. The flat top surfaces of the bumps form the actual regions of contact with the mating contacts on the substrate.

Contact bumps are also sometimes included in chip scale packages. In general, a "chip scale package" or "chip size package" refers to a package that includes a bare die along with one or more packaging elements. For example, chip scale packages can include thin protective members attached to the face, sides or backside of the die. In addition, chip scale packages can include contact bumps similar to the bumps on bumped dice. Some persons skilled in the art consider a bumped die the simplest form of a chip scale package.

With bumped dice and chip scale packages, it is sometimes necessary to make non-bonded, or temporary, electrical connections with the contact bumps. For example, in the production of Known Good Die (KGD), semiconductor manufacturers are required to test bumped dice prior to shipment. Temporary packages can be used to house a single bare die, or a chip scale package, for burn-in and other test procedure. These types of temporary packages are disclosed in U.S. Pat. Nos. 5,519,332; 5,541,525; 5,495,179; 5,440,240; and 5,408,190 to Wood et al.

Interconnects associated with the temporary packages can be used to electrically contact the bumps on the dice, or on the chip scale packages. With one type of interconnect, indentations on the interconnect can be sized to retain and electrically contact the bumps. For example, this type of interconnect can include a multi layered tape, similar to TAB tape manufactured by Nitto Denko and others. The tape can include a polyimide layer formed with patterns of indentations, and a metal layer subjacent to the indentations. The bumps fit into the indentations and electrically contact the metal layer.

To assist in making this temporary electrical connection, a temporary package can also include a force applying mechanism, such as a spring, adapted to bias the semiconductor component against the interconnect. A contact force must be generated by the force applying mechanism that is sufficient to break through the native oxide covering the bumps. If a sufficient contact force is not generated, then the resultant electrical connection can be poor. However, it is also advantageous to maintain this contact force as low as possible to avoid excessive deformation of the bumps. In particular, the loaded bumps exhibit creep during the burn-in cycles, which are typically performed at elevated temperatures for several hours or more.

In the past, following testing of dice with contact bumps, it has been necessary to reflow the bumps, which are typically damaged by the test procedure. This is an additional process step which adds to the expense and complexity of the testing process. Furthermore, it requires heating the tested dice which can adversely affect the integrated circuitry formed thereon.

Another consideration in testing bumped dice and chip scale packages is the dimensional variations between the contact bumps. The interconnect must be able to accommodate dimensional variations between bumps on different dice or packages, and dimensional variations between individual bumps on the same die or package. These dimensional variations can include the diameter, height, shape, and location of the bumps. In particular, the diameter and z-dimension location (planarity) of the bumps can make the electrical connections difficult to make without high contact forces.

Trapped gases can also cause problems during a reflow procedure. For example, gases can be trapped between the bumps and indentations and in cavities formed within the bumps. These trapped gas can expand during a reflow connection process causing the solder material to splatter.

In view of the foregoing, improved methods, apparatus and systems for making electrical connections to bumped semiconductor components are needed.

SUMMARY OF THE INVENTION

In accordance with the present invention, an improved method, apparatus and system for testing semiconductor components having contact bumps are provided. The semiconductor components can be singulated bumped dice, bumped dice contained on a semiconductor wafer, or bumped chip scale packages. The method is performed with an interconnect adapted to establish temporary electrical communication with the contact bumps on the semiconductor components.

Several different embodiments of the interconnect are provided. For a die level test system, the interconnect can be configured for use with a burn-in board for testing one or more singulated dice, or one or more chip scale packages. For a wafer level test system, the interconnect can be configured for use with a wafer handler for testing multiple or single dice on a wafer, up to an entire wafer. In each embodiment test signals can be applied through the interconnect to test the semiconductor devices contained on the dice, packages or wafers.

The interconnect comprises a substrate with patterns of contact members and associated conductors. Each contact member comprises one or more projections, configured to retain and electrically contact an individual contact bump. The projections can include an electrically conductive layer, and sharp edges for penetrating native oxide layers covering the contact bumps. The projections can be formed integrally with the substrate using an etching process, or can be added features formed by deposition, lamination or other additive process. In the illustrative embodiments, there are one to five projections per contact member. In addition, the projections can be configured to accommodate dimensional variations in the contact bumps, and variations in the planarity (i.e., z-direction location) of a pattern of bumps. Still further, the projections minimally deform the contact bumps and can be configured to require a minimal amount of contact force.

The die level test system includes an interconnect configured for electrical connection to a testing apparatus, such as a burn-in board, in electrical communication with test circuitry. The interconnect can be used to simultaneously test multiple bare dice, or chip scale packages. In addition, a force applying mechanism can include clips that attach to the interconnect, and a biasing member such as a spring, elastomer, or fluid filled bladder, for biasing the dice or packages, against the interconnect.

In the wafer level test system, an interconnect can be mounted to a probe card fixture of a conventional testing apparatus, such as a wafer handler. During a test procedure, test circuitry associated with the testing apparatus can apply test signals through the interconnect to the integrated circuits on the dice. In addition, the test signals can be electronically switched as required to selected dice on the wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a plan view of a prior art bumped semiconductor die including contact bumps arranged in a ball grid array (BGA);

FIG. 1B is a cross sectional view of a prior art contact bump taken along section line 1B--1B of FIG. 1A;

FIG. 1C is a graph illustrating a sampling of a prior art bumped semiconductor dice wherein an average minimum bump diameter (D.sub.MIN) and an average maximum bump diameter (D.sub.MAX) are ascertained;

FIG. 1D is a schematic cross sectional view of a prior art chip scale package having contact bumps;

FIG. 1E is a schematic cross sectional view of another prior art chip scale package having contact bumps;

FIG. 2 is a schematic plan view of an interconnect constructed in accordance with the invention;

FIG. 3 is an enlarged perspective view of a contact member for the interconnect shown in FIG. 2;

FIG. 3A is an enlarged perspective view of an alternate embodiment contact member having three projections;

FIG. 3B is an enlarged perspective view of another alternate embodiment contact member having five projections;

FIG. 4A is an enlarged cross sectional view of a projection for the contact member of FIG. 3A taken along section line 4A--4A of FIG. 2;

FIG. 4B is an enlarged cross sectional view equivalent to FIG. 4A of an alternate embodiment projection formed using an isotropic etch process;

FIG. 4C is an enlarged cross sectional view equivalent to FIG. 4A of an alternate embodiment projection formed using a deposition process;

FIG. 5A is an enlarged plan view of the contact member of FIG. 3;

FIG. 5B is a cross sectional view taken along section line 5B--5B of FIG. 5A;

FIG. 5C is a cross sectional view equivalent to FIG. 5B illustrating an alternate spacing for the projections;

FIG. 6A is an enlarged schematic perspective view of an alternate embodiment contact member having one projection;

FIG. 6B is an enlarged plan of the projection shown in FIG. 6A;

FIG. 6C-6E are enlarged plan views of exemplary self centering patterns for the contact member shown in FIG. 6A;

FIG. 7 is an enlarged plan view of an alternate embodiment interconnect fabricated with microbump contact members;

FIG. 7A is a cross sectional view of a microbump contact member taken along section line 7A--7