Optoelectronic smart pixel array for a reconfigurable intelligent optical interconnect

Claims

We claim:

1. A packaged opto-electronic data switching means comprising

a plurality of optical channel input means, each comprising an optical-to-electronic signal converter for conversion of optical signals received at said optical channel input means to corresponding electrical signals;

a plurality of optical channel output means, each comprising an electrical-to-optical signal converter for conversion of electrical signals received at said optical channel output means into corresponding optical signals;

an electrical injector channel input means;

an electrical extractor channel output means;

control input means for inputting control signals;

an extractor-selector data switching means operably connected to said optical channel input means and said electrical extractor channel output means, said extractor-selector data switching means to receive electrical signals from said optical channel input means and switch a subset of said received electrical signals to said electrical extractor channel output means responsive to control signals;

an injector-selector data switching means operably connected to said electrical injector channel input means, and said optical channel output means, for switching electrical signals from said optical channel input means and said electrical channel input means, to said optical channel output means in response to control signals;

a mechanical substrate comprising a plurality of electrical conductors, wherein said extractor-selector data switching means is interconnected to said optical channel input means and said electrical extractor channel output means by way of electrical conductors on said substrate, and said injector-selector data switching means is connected to said electrical injector channel input means, and said optical channel output means by way electrical conductors on said substrate;

and a packaging means suitable for mounting said opto-electronic data switching means onto a substantially larger processing module, said packaging means packaging said optical channel input means, said output channel output means, said control input means, said electrical injector-channel input means, said electrical extractor-channel output means, said injector-selector data switching means, said extractor-selector data switching means and said substrate,

thereby providing a packaged opto-electronic data switching means which supports controllable switching of data received on incoming electronic injector channel at said electronic injector channel input means onto outgoing optical channels at said plurality of optical channel output means and controllable switching of data received on incoming optical channels at said plurality of optical channel input means onto outgoing electrical extractor channel at said electrical extractor channel output means.

2. The packaged opto-electronic data switching means of claim 1, further comprising

a data processing means operably connected to said control input means, said extractor-selector data switching means and at least one of said plurality of optical channel input means, said data processing means operable to receive data from said optical channel input means, process said data and generate control signals for controlling said extractor-selector data switching means.

3. The packaged opto-electronic data switching means of claim 2 further comprising

a second data processing means operably connected to said optical channel input means and injector-selector data switching means, said second data processing means operable to process data received on at least one of said plurality of optical channel input means and modify said data, whereby said injector-selector data switching means switches modified values of said data onto at least one of said plurality of optical channel output means.

4. The packaged opto-electronic data switching means of claim 2 wherein

said data processing means processes packets of data received on at least one of said optical channel input means by performing any series of boolean logic operations involving bits from packet and bits from a control bit pattern and generates control signals for said extractor-selector data switching means to extract selected packets based on said processing.

5. The packaged opto-electronic data switching means of claim 2 wherein

said data processing means comprises silicon substrate based processing means and

at least one of said plurality of optical channel output means comprises at least one of a Self-Electro Optical Device (SEED) and a Vertical Cavity (VCSEL) electrical-to-optical signal converter.

6. The packaged opto-electronic data switching means of claim 1, further comprising

data storage means operably connected to said plurality of optical channel input means, for buffering electrical signals from said plurality of optical channel input means.

7. The packaged opto-electronic data switching means of claim 1, further comprising

a first data storage means operably connected to said optical channel input means for storing data received on said optical channel input means responsive to control signals,

a second data storage means operably connected to said electrical injector channel input means for storing data received on said electrical injector channel input means responsive to control signals,

a data processing means operably connected to at least one of said first and second data storage means, responsive to control signals for generating control signals for at least one of said first and second data storage means.

8. The packaged opto-electronic data switching means of claim 7 wherein

said optical channel input and output means are clocked at an optical clock rate,

said electrical channel input and output means are clocked at first and second electrical clock rates, respectively,

wherein optical clock rate exceeds both first and second electrical clock rates.

9. The packaged opto-electronic data switching means of claim 1 wherein said substrate further comprises a multi-chip module substrate.

10. A processing system comprising: a plurality of packaged opto-electronic data switching means as claimed in claim 1;

a plurality of processing modules each operably connected to at least one of said packaged opto-electronic data switching means,

a plurality of optical imaging means, each one coupling one of said opto-electronic data switching means to another one of said opto-electronic data switching means, so that optical signals from an optical channel output means of at least one of said packaged opto-electronic data switching means is imaged onto optical channel input means of another one of said packaged opto-electronic data switching means,

thereby establishing controllable optical communication channels between said processing modules.

11. The system of claim 10 wherein

at least one of said optical imaging means comprises at least one of a fiber image guide means and a parallel fiber ribbon means.

12. A packaged opto-electronic device comprising:

a plurality of optical input ports, each comprising an optical-to-electronic signal converter for conversion of optical signals received at said an optical input port to corresponding electrical signals;

a plurality of optical output ports, each comprising an electrical-to-optical signal converter for conversion of electrical signals received at said optical output port into corresponding optical signals;

an electrical input port;

an electrical output port;

a controllable first data switch operably connected to said optical input ports and said electrical output port, said first data switch to receive electrical signals from said optical input ports and switch a subset of said received electrical signals to said electrical output port responsive to control signals;

a controllable second data switch for switching electrical signals from said optical input ports and said electrical input port, to said optical output ports in response to control signals, said second data switch operably connected to said electrical input port, and said optical output ports;

an integrated circuit substrate comprising a plurality of electrical conductors, wherein said first data switch is interconnected to said plurality of optical channel input ports and said electrical output port by way of electrical conductors on said substrate, and said second data switch is connected to said electrical input port, and said plurality of optical output ports by way of electrical conductors on said substrate; and

a package suitable for mounting said device onto a substantially larger processing module, said package packaging said plurality of optical input ports, said plurality of optical output ports, said electrical input port, said electrical output port, said first data switch, said second data switch and said substrate.

13. The opto-electronic device of claim 12, further comprising:

a control input port for receiving control signals to control at least one of said first data switch and said second data switch.

14. The opto-electronic device of claim 13, further comprising

a control output port, for outputting control signals to said substantially larger processing module.

15. The opto-electronic device of claim 13, further comprising:

a control signal storage circuit operably connected to at least one of said first data switch and said second data switch, for storing controlling signals controlling at least one of said first data switch and said second data switch.

16. The opto-electronic device of claim 15, further comprising:

a control processing circuit in communication with said control input port and operably connected to said control signal storage circuit, said control processing circuit operable to generate control signals to be stored in said control signal storage circuit, responsive to control signals at said control input port.

17. The opto-electronic device of claim 16, wherein

said control processing circuit is in communication with at least one of said optical input ports, to process signals from said optical input ports and determine control signals to be stored in said control signal storage circuit, thereby controlling at least one of said first and second data switch.

18. A computing system comprising:

a first and second opto-electronic device each as claimed in claim 17; and

an optical imaging means, imaging optical signals from each one optical output port of said first opto-electronic device to a corresponding optical input port of said second opto-electronic device.

19. A computing system comprising:

a plurality of opto-electronic devices, each as claimed in claim 15, interconnected in an optical ring;

a plurality of optical imaging means interconnecting at least one optical output port of each one of said opto-electronic devices to at least one corresponding optical input port of another one of said plurality of opto-electronic devices to form said optical ring.

20. The computing system as claimed in claim 19,

wherein one optical input port of each of said plurality of opto-electronic devices is operably connected to receive an optical clock signal from another opto-electronic device, and one optical output port is operably connected to transmit an optical clock signal to another opto-electronic device.

21. The computing system as claimed in claim 19,

wherein at least one of said plurality of optical imaging means comprises one of a two dimensional fiber ribbon, and an optical image guide.

22. The opto-electronic device of claim 12, further comprising:

a plurality of first input data storage circuits, each one of which is operably connected to an associated one of said optical-to-electrical signal converters, for buffering electrical signals from said associated one of said optical-to-electrical signal converters.

23. The opto-electronic device of claim 22, further comprising

a data processing circuit operably connected to said second data switch and at least one of said optical input ports, by way of at least one of said first input data storage circuits, said data processing circuit operable to receive data from an interconnected optical input port and modify said received data, so that said second switch switches data modified by said data processor to at least one of said optical output ports.

24. The opto-electronic device of claim 12, further comprising:

a plurality of second input data storage circuits, each one of which is operably connected to an associated one of said electrical input ports, for buffering incoming electrical signals at said associated one of said electrical input ports.

25. The opto-electronic device of claim 12, further comprising

a data processing circuit operably connected to said second data switch and at least one of said optical input ports, operable to receive data from an interconnected optical input port and modify said received data, so that said second switch switches data modified by said data processor to at least one of said optical output ports.

26. The opto-electronic device of claim 25, wherein said data processing circuit modifies at least some of said received data using parallel prefix computations.

27. The opto-electronic device of claim 12, wherein

said optical input ports and said optical output ports are each clocked at an optical clock rate;

said electrical input port and said electrical output port are clocked at first and second electrical clock rates, respectively;

and wherein said optical clock rate exceeds both said first and second electrical clock rates.

28. The opto-electronic device of claim 12, wherein

said integrated circuit substrate comprises silicon; and

wherein each of said optical-to-electrical signal converters comprises at least one of a Self-Electro Optical Device (SEED) and a Vertical Cavity Surface Emitting Laser (VCSEL).

29. A computing system comprising an opto-electronic device as claimed in claim 12.

30. A computing system comprising:

a first and second opto-electronic device as claimed in claim 12; and

an optical imaging means, imaging optical signals from each one optical output port of said first opto-electronic device to a corresponding optical input port of said second opto-electronic device.

31. A packaged opto-electronic device comprising:

a plurality of optical input ports, each comprising an optical-to-electronic signal converter for conversion of optical signals received at said an optical input port to corresponding electrical signals;

a plurality of optical output ports, each comprising an electrical-to-optical signal converter for conversion of electrical signals received at said optical output port into corresponding optical signals;

at least one electrical input port;

at least one electrical output port;

a controllable first data switch operably connected to at least one of said plurality optical input ports and said at least one electrical output port, said first data switch to receive electrical signals from said plurality of optical input ports and switch a subset of said received electrical signals to said at least one electrical output port responsive to control signals;

a controllable second data switch for switching electrical signals from said plurality of optical input ports and said at least one electrical input port, to said optical output ports in response to control signals, said second data switch operably connected to said at least one electrical input port, and at least one of said optical output ports;

a control input port for receiving control signals to control at least one of said first data switch and said second data switch;

a control signal storage circuit operably connected to at least one of said first and second data switch, for storing control signals controlling at least one of said first and second data switch;

a control processing circuit in communication with said control input port and operably connected to said control signal storage circuit, said control processing circuit operable to generate control signals to be stored in said control signal storage circuit, responsive to control signals at said control input port,

wherein said control processing circuit is in communication with at least one of said optical input ports, to process signals from said at least one of optical input ports and determine control signals to be stored in said control signal storage circuit, thereby controlling at least one of said first and second data switch;

an integrated circuit substrate comprising a plurality of electrical conductors, wherein said first data switch is interconnected to said plurality of optical channel input ports and said at least one electrical output port by way of electrical conductors on said substrate, and said second data switch is connected to said at least one electrical input port, and said plurality of optical output ports by way electrical conductors on said subtrate; and

a package suitable for mounting said device onto a substantially larger processing module, said package packaging said plurality of optical input ports, said plurality of optical output ports, said at least one electrical input port, said at least one electrical output port, said first data switch, said second data switch, said control input port, said control signal storage circuit, said control processing circuit and said substrate.

32. The opto-electronic device of claim 31, wherein

said optical input ports and said optical output ports are clocked at an optical clock rate;

said at least one electrical input port and said at least one electrical output port are clocked at first and second electrical clock rates, respectively;

and wherein said optical clock rate exceeds both said first and second electrical clock rates.

33. A packaged opto-electronic device comprising:

an optical input port, comprising an optical-to-electronic signal converter for conversion of optical signals received at said optical input port to corresponding electrical signals;

an optical output port, comprising an electrical-to-optical signal converter for conversion of electrical signals received at said optical output port into corresponding optical signals;

an electrical input port;

an electrical output port;

a controllable first data switch operably connected to said optical input port and said electrical output port, said first data switch to receive electrical signals from said optical input port and switch a subset of said received electrical signals to said electrical output port responsive to control signals;

a controllable second data switch for switching electrical signals from said optical input port and said electrical input port, to said optical output port in response to control signals, said second data switch operably connected to said electrical input port, and said optical output port;

a control input port for receiving control signals to control at least one of said first data switch and said second data switch;

a control signal storage circuit operably connected to at least one of said first and second data switch, for storing control signals controlling at least one of said first and second data switch;

a control processing circuit in communication with said control input port and said optical input port, and operably connected to said control signal storage circuit, said control processing circuit operable to generate control signals to be stored in said control signal storage circuit, responsive to control signals at said control input port and signals at said optical input port, thereby controlling at least one of said first and second data switch;

a data processing circuit operably connected to said second data switch and said optical input port, operable to receive data from said optical input port and modify said received data, so that said second data switch switches data modified by said data processor to said optical output port;

an integrated circuit substrate comprising a plurality of electrical conductors, wherein said first data switch is interconnected to said optical channel input ports and said electrical output port by way of electrical conductors on said substrate, and said second data switch is connected to said electrical input port, and said optical output port by way electrical conductors on said substrate; and

a package suitable for mounting said device onto a substantially larger processing module, said package packaging said optical input port, said optical output port, said electrical input port, said electrical output port, said first data switch, said second data switch, said control input port, said control signal storage circuit, said control processing circuit, said data processing circuit and said substrate.

34. The opto-electronic device of claim 33, wherein said data processing circuit modifies at least some of said received data using parallel prefix computations.

35. The opto-electronic device of claim 33, wherein

said optical input port and said optical output port are clocked at an optical clock rate;

said electrical input port and said electrical output port are clocked at first and second electrical clock rates, respectively;

and wherein said optical clock rate exceeds both said first and second electrical clock rates.

BACKGROUND

1. Field of Invention

This invention relates to the design of reconfigurable intelligent photonic interconnect, in particular to the design and packaging of an opto-electronic data processing and switching means called a "smart pixel array" which make possible the realization of a reconfigurable intelligent optical interconnect which implements multiple reconfigurable optical communication channels. The multiple reconfigurable optical channels can simultaneously support multiple "one-to-one", "one-to-many", "one-to-all" and "many-to-many" broadcast communication patterns and can be reconfigured dynamically.

2. Discussion of Prior Art

A literature and patent search did not reveal any prior art in optoelectronic data processing and switching means for the reconfigurable intelligent optical backplanes and interconnect as proposed in this application. A discussion of prior arts based on electrical and optical backplanes will be given.

In a computer system a bus is an interconnection topology commonly used to communicate between plug-in modules in the form of a printed circuit board (PCB). The plug-in modules connect to a common communication media (i.e., the bus) on the backplane printed circuit board. The rules that govern the access of the modules to the bus and the data transfers constitute the bus protocol. A typical implementation of a bus includes a set of metal traces embedded in a backplane PCB. Plug-in modules connect to the bus through edge connectors and drive the bus through high power bus transceivers. Modules connected to the bus all reside on the same backplane PCB. Various standards have been developed which define the physical features of the backplane PCB, the mechanical packaging structure and the bus protocols. These bus standards include VME, FutureBus+, Multibus and Nubus standards and typical standards are described in a textbook by J. Di Giacom, "Digital Bus Handbook", McGraw Hill.

There are many practical limitations to the use of the bus topologies. In the backplane PCB implementing a bus, each metal trace electronically interconnects all plug-in modules. A typical backplane PCB based upon a standardized 19 inch wide rack (the commercial VME and FutureBus standards) houses approximately 20 plug-in modules. To transfer data a single plug-in module must act as a bus master. Distributed protocols are used to arbitrate between contending plug-in modules to appoint the bus-master. To transfer data a bus-master must insert the information including address information and data in a series of individual word transfers over the bus. Typically each word contains 32 bits and the duration of the word transfer is determined by the nature of the bus protocol.

When transferring data the master plug-in module must drive the bus traces on the backplane PCB which in turn must drive all the plug-in modules inserted into the backplane PCB, which can be as high as 20 plug-in modules. The capacitive loading on a bus due to the attached modules greatly increases the propagation delay. This directly affects the data transfer rate in most types of data transfer protocols, for example synchronous protocols in which data transfers are centrally clocked, and in compelled asynchronous protocols which require a handshake on every data transfer. The only data transfer which is not heavily impacted by the bus round trip delay caused by capacitive loading is the uncompelled source synchronous bus transfers in which a long burst transfer is clocked by the sender. In such a transfer the data transfer rate is primarily limited by skews between bits and strobe.

The capacitive loading also decreases the impedance of a bus line to a very low value, i.e., approximately 20 ohms. Since a bus driver sees half the bus impedance i.e. 10 ohms, high currents are required to drive the bus at full speed. For example, a 3 volt swing on a bus which is typical for TTL will require 300 milliAmps (3 volts divided by 10 ohms) to drive the bus on the first transition with proper termination. Since most bus drivers are rated at only 50 to 100 MA the bus is typically under terminated and dependent upon multiple reflections to build up the signal to the final level. The reflections take one or more bus round trip delays to settle resulting in a settling time delay that is a significant portion of the transfer cycle time for a bus.

These limitations limit the aggregate bandwidth of the FutureBus+ to approx. 3.2 GByte/sec or 25.6 Gbit/sec, i.e., the sum of all data communications between plug-in modules cannot exceed approx. 25.6 Gbit/sec since this is the maximum capacity of the bus. In addition to low bandwidths, electronic busses suffer from other limitations. Electronic busses lack multiple independent channels and thus they cannot provide the parallelism required by large scale parallel computing and communication systems. Finally, electronic busses are not scalable to interconnect hundreds of plug-in modules since the increasing capacitance, inductance and impedance problems of a larger bus will lower the already low bandwidth of the bus.

These limitations of electrical busses have not gone unnoticed. In U.S. Pat. No. 5,122,691 Balakrishnan describes a bus architecture which reduces the bus round trip delay by incorporating the busses on an integrated circuit called the bus IC. The plug-in modules have point-to-point links connecting them to the bus ICs. These point-to-point links have a relatively small capacitive load so high power bus transceivers are not required. The bus protocol of the system remains unchanged, i.e. a distributed bus protocol such as the FutureBus+ protocol is used to determine a bus master which transfers data over the bus to one or more bus slaves in a series of individual word transfers according to the protocol. However, the bus transfers are now faster due to the decreased capacitive loading, typically by a factor of 2 or 3.

There are number of problems with Balakrishnan's architecture. First, the bus still supports a single channel where all plug-in modules compete for access to the single channel. At most two plug-in modules can communicate over the bus simultaneously, and the individual word transfers over the bus are still sequential--the improvement over the existing bus performance is a factor of 2 or 3. The bus is electrical and as a result it will always suffer from capacitance, inductance and impedance problems. Finally, it is not scalable to interconnect hundreds of plug-in modules.

Current large communication and computing systems have communications requirements in the hundreds of Gigabits/sec or more. The Cray T3D supercomputer communication mechanism is described in "CRAY T3D System Architecture Overview", Sep. 23, 1993, available from Cray Research, Chippewa Falls, Wis. The electronic bus is far too slow to meet the communication demands of a large computing system. In the Cray system processors reside on PCB modules and the modules are interconnected in the form of a 3 dimensional mesh which occupies many large cabinets. Every node has a direct electronic communication link to two nearest neighbors in each of three dimensions. Each communication link is a point-to-point datapath with 16 bits of data and 8 bits of control. The link is clocked at rates of 150 Mbit/per sec., so that the link has a point-to-point data bandwidth of 2.4 Gbit/sec. A large T3D supercomputer may consist of 1,024 nodes arranged in a 8.times.8.times.16 mesh. The bisection bandwidth of a network is defined as the bandwidth which crosses a bisector which cuts the network into two halves of equal size. If we cut the mesh into two equal size smaller meshes of size 8.times.8.times.8, there are 128 communication links joining these two halves. (This figure includes 64 links between the inner sides of the two halves and 64 links which join the outer sides of the two halves). Hence, the bisection bandwidth of the Cray T3D is 128 links times 2.4 Gbit/sec per link or equivalently 307 Gbit/sec.

However, there are many limitations to the electronic interconnects used in current large scale computing and communication networks. These networks have much more bandwidth than a bus by providing multiple independent high bandwidth communication channels. However, the cost of these multiple channels is a large number of electronic wires between cabinets and electronic traces on PCBs. The inductance and capacitance of these wires and traces necessitates the use of high power transceivers which consume large amounts of power. The inductance and capacitance of these channels also limits the maximum clock rate to at best a few hundred Mbit/sec. The electrical channels are also susceptible to electromagnetic interference.

Hamanka describes a passive optical bus in "Optical bus interconnection system using Selfoc lenses", Optics Letters, Vol. 16, No. 16, Aug. 15, 1991. In this passive optical bus the electronic bus transceivers of the plug-in modules of an electronic bus are replaced by optical bus transceivers. The receiving circuit in an electrical backplane is replaced by a photodetector array. The transmitting circuit in an electrical backplane is replaced by a light modulator. The communication medium responsible for the transferring of data is changed from metal traces on a backplane PCB to optical paths through free-space or an optical medium.

However, Hamanaka's passive optical bus still suffers from many disadvantages associated with the electronic bus. The optical bus still supports a single communication channel so that data transfers still occur sequentially over the bus. Hamanaka's passive optical bus does not implement multiple independent optical channels. A data transfer requires the same steps as in an electrical backplane. A bus master is first selected and the bus master then broadcasts data over the optical bus which must be received by all plug-in module PCBs. These PCBs then must perform packet processing to determine whether the packet is addressed to them. This architecture requires that every plug-in module PCB must be able to monitor all data on the optical bus. The limitation that every PCB must monitor all the data on the optical bus will limit the rate at which data can be transmitted over the bus to the rate at which every PCB can receive and process the data.

An integrated circuit (IC) has a limited electronic Input/Output IO bandwidth of typically tens of Gigabits/second due to IC packaging constraints. Each IC package has at most approx. 500 hundred IO pins due to constraints associated with the connections between the IC substrate and the IC package. A discussion of IC packaging limitations is given in L. L. Moresco, "Electronic System Packaging: The Search for Manufacturing the Optimum in a Sea of Constraints", IEEE Transactions on Components, Hybrids, and Manufacturing Technology", Vol. 13, No. 3, September 1990. Two common techniques to interconnect an integrated circuit VLSI die with a package are "wire-bonding" and "tape automated bonding". These techniques are described in R. R. Tummala and E. J. Rymaszewski (Ed.), "MicroElectronics Packaging Handbook", Reinhold, 1989. Each IO pin has a maximum clock rate of typically a few hundred Mbits/second due to capacitance and inductance and crosstalk associated with the connections between the die and the package. The maximum IO bandwidth of a single IC package is the product of the number of pins times the clock rate per pin. The maximum IO bandwidth of a packaged IC is typically in the tens of Gigabits/second.

Hamanaka's architecture requires that optical signals be received on a photodetector array, all converted to electronics, and all routed off the array to an electronic IC for further processing. Hence, the peak bandwidth of Hamanaka's passive optical bus architecture will be limited to the