Test system with mechanical alignment for semiconductor chip scale packages and dice

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FIELD OF THE INVENTION

This invention relates generally to testing of semiconductor components, such as chip scale packages and bare dice. More particularly, this invention relates to a test system with mechanical alignment and to a method for fabricating the test system.

BACKGROUND OF THE INVENTION

A recently developed semiconductor package is known as a "chip scale package" or a "chip size package". The dice contained in these packages are referred to as being "minimally packaged". Chip scale packages can be constructed in "cased" or "uncased" configurations. Cased chip scale packages have a peripheral outline that is slightly larger that an unpackaged die. Uncased chip scale packages have a peripheral outline that is about the same as an unpackaged die.

Typically, a cased chip scale package includes a substrate formed of plastic, ceramic, or other electrically insulating material bonded to the face of the die. The substrate can include external contacts for making outside electrical connections to the chip scale package. For example, the external contacts for a chip scale package can comprise contact bumps arranged in a ball grid array (BGA), or a fine ball grid array (FBGA). Typically, the external contacts comprise a solder material, that permits the chip scale package to be flip chip bonded to a printed circuit board, or other substrate. Uncased chip scale packages can include external contacts formed directly on the device bond pads in the manner of a bumped die.

Following the manufacturing process, chip scale packages must be tested and burned-in. Test apparatus can be used to house one or more chip scale packages for testing, and to make temporary electrical connections with the external contacts on the chip scale packages. The test apparatus can include an interconnect component having contact members adapted to make the temporary electrical connections with the external contacts on the chip scale packages.

For making the electrical connections the contact members on the interconnect must be aligned with the external contacts on the chip scale packages. One method of alignment is with an optical alignment system such as described in U.S. Pat. No. 5,634,267 to Wood et al. Another method of alignment is with a mechanical alignment system.

The present invention is directed to a test system with an improved mechanical alignment system. The test system can be used to test chip scale packages or other semiconductor components such as bare semiconductor dice.

SUMMARY OF THE INVENTION

In accordance with the present invention, a test system for semiconductor components, and a method for fabricating the test system are provided. The components can be chip scale packages, or bare semiconductor dice, having external contacts in the form of contact bumps.

The test system includes a base for retaining one or more components, and multiple interconnects having contact members for making temporary electrical connections with the external contacts on the components. The test system also includes a mechanical alignment fixture having alignment surfaces for aligning the components to the interconnects. A single alignment fixture can be formed on the base, or separate alignment fixtures can be formed on each interconnect. In addition to the alignment fixture, the components can include alignment members configured to interact with the alignment surfaces on the alignment fixture and guide the components into alignment with the interconnects. Illustrative alignment members include beveled edges, alignment bumps, and alignment posts formed on the components.

Several different embodiments of alignment fixtures are disclosed. In each embodiment the alignment fixtures include alignment surfaces of a desired configuration. For example, the alignment surfaces can include openings in the alignment fixtures sized to engage the alignment members on the components. The alignment surfaces can also be configured for engaging the edges of the components, or for engaging the contact bumps on the components. Still further, the alignment surfaces can be configured for a two stage alignment procedure including a coarse alignment stage and a fine alignment stage. In the two stage embodiment, a first layer of the alignment fixture can provide a first surface for coarse alignment, while a second layer of the alignment fixture can provide a second surface for fine alignment.

The alignment fixture can comprise a polymeric material, such as a thick film resist, which is deposited on the interconnects, developed with alignment surfaces, and then cured. Preferably, the thick film resist is deposited on a wafer that includes multiple interconnects, which are singulated following development and curing of the resist. Alternately, the alignment fixture can comprise a polymer tape applied to the interconnects in a desired pattern. As another alternative, the alignment fixture can comprise a separate plate attached to the interconnects, or to the base of the system.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic side elevation view of a prior art component in the form of a bumped semiconductor die;

FIGS. 1B and 1C are schematic cross sectional views of prior art components in the form of chip scale packages;

FIG. 2A is a schematic perspective view of a test system constructed in accordance with the invention and illustrated in an unassembled configuration;

FIG. 2B is a schematic perspective view of an alternate embodiment test system illustrated in an assembled configuration;

FIG. 3 is a schematic perspective view of an interconnect component for the test system of FIG. 2A or 2B;

FIG. 3A is an enlarged cross sectional view taken along section line 3A--3A of FIG. 3 illustrating a contact member of the interconnect;

FIGS. 4A and 4B are enlarged cross sectional views of an alternate embodiment contact member;

FIG. 5 is a schematic side elevation view of a semiconductor component having alignment members in the form of beveled edges;

FIG. 5A is a bottom view taken along section line 5A--5A of FIG. 5;

FIG. 6 is a schematic side elevation view of a semiconductor component having alignment members in the form of alignment bumps;

FIG. 6A is a bottom view taken along section line 6A--6A of FIG. 6;

FIG. 7 is a schematic side elevation view of a semiconductor component having alignment members in the form of alignment posts;

FIG. 8A is a schematic cross sectional view taken along section line 8A--8A of FIG. 2A illustrating an alignment fixture of the system during alignment of a component of FIG. 5;

FIG. 8B is a schematic cross sectional view equivalent to FIG. 8A illustrating an alternate embodiment alignment fixture during alignment of the component of FIG. 6;

FIG. 8C is a schematic cross sectional view equivalent to FIG. 8A illustrating an alternate embodiment alignment fixture during alignment of the component of FIG. 7;

FIG. 8D is a schematic cross sectional view equivalent to FIG. 8A illustrating an alternate embodiment alignment fixture during alignment of the component of FIG. 1A; and

FIG. 8E is a schematic cross sectional view equivalent to FIG. 8A illustrating an alternate embodiment alignment fixture during alignment of the component of FIG. 1A.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIGS. 1A-1C, prior art semiconductor components are illustrated. In FIG. 1A, a bumped semiconductor die 10 includes a pattern of contact bumps 12. Typically the contact bumps 12 are arranged in a dense array. By way of example, the contact bumps 12 can be arranged in a ball grid array (BGA), or a fine ball grid array (FBGA). The contact bumps 12 are in electrical communication with various semiconductor devices and integrated circuits formed on the die 10.

The contact bumps 12 can be formed by processes that are known in the art, such as electro-deposition, and ball limiting metallurgy (BLM). Typically, the contact bumps 12 comprise a solder alloy. Representative solder alloys for the contact bumps 12 include 95%Pb/5%Sn, 60%Pb/40%Sn, 63%In/37%Sn, 100%Sn, and 62%Pb/36%Sn/2%Ag. Each contact bump 12 can be generally hemispherical, convex, or dome-shaped, with an outside diameter "D" and a height of "H". Representative size ranges for the diameter "D" and height "H" can be from about 2.5 mils to 30 mils.

Referring to FIG. 1B, a die 10A can also be contained within a chip scale package 14A. The chip scale package 14A comprises a BGA substrate 16 bonded to the face of the die 10A with an adhesive layer 18. The BOA substrate 16 includes contact bumps 12 in electrical communication with the contact bumps 12 on the die 10A. The contact bumps 12 on the BGA substrate 16 are substantially equivalent to the contact bumps 12 (FIG. 1A) previously described.

Referring to FIG. 1C, a chip scale package 14B comprises a semiconductor die 10B, and protective members 20 bonded to either side of the die 10B. In addition, the chip scale package 14B includes contact bumps 12 in electrical communication with the die bond pads via leads 22. An encapsulant 24 and an elastomeric pad 26 electrically isolate the leads 22 and the contact bumps 12. As is apparent, these configurations are merely exemplary and other chip scale package configurations are known in the art.

Referring to FIG. 2A, a test system 28 constructed in accordance with the invention is illustrated. The test system 28 is configured to test multiple semiconductor components 30A. The test system 28 includes a base 32 configured to retain the components 30A. The base 32 includes external contacts 34 configured for mating electrical engagement with a test apparatus 52, such as a burn-in board. The test apparatus 52 is in electrical communication with test circuitry 54. The test circuitry 54 is configured to apply test signals to the integrated circuits contained on the components 30A and to analyze the resultant signals.

The test system 28 also includes multiple interconnects 36 mounted to the base 32. The interconnects 36 include patterns of contact members 38 configured to form non-bonded, temporary electrical connections, with the contact bumps 12 on the components 30A. In addition, the test system 28 includes a force applying mechanism 40 configured to bias the components 30A against the interconnects 36. In the illustrative embodiment, the force applying mechanism comprises a bridge clamp 42 having clip portions 44 attachable to the base 32, and leaf springs 46 attached to the bridge clamp 42.

The test system 28 also includes a mechanical alignment fixture 48 configured to align the components 30A to the interconnects 36. In the illustrative embodiment, the alignment fixture 48 comprises a polymer fence formed on the base 32 and interconnects 36. The alignment fixture 48 includes alignment surfaces in the form of alignment openings 50. Each alignment opening 50 can be sized and shaped to contact alignment members 72A on the components 30A to be hereinafter described. Alternately, the alignment openings 50 can be configured to contact outside edges of the components 30A, or to contact the contact bumps 12 on the components 30A.

Referring to FIG. 2B, an alternate embodiment test system 28A includes a force applying mechanism 40A with elastomeric spring members 46A. The elastomeric spring members 46A can be formed of a material such as silicone, butyl rubber, or fluorosilicone. Suitable elastomeric materials include "PORON" available from Rogers. The elastomeric spring members 46A can be secured to the bridge clamp 42 using an adhesive such as silicone. One suitable adhesive is "ZYMET" silicone elastomer manufactured by Zymet, Inc., East Hanover, N.J. Rather than being formed of elastomeric materials, the spring members 46A can be formed as compressible gas filled bladders. This type of bladder is available from Paratech of Frankfort, Ill. under the trademark

Referring to FIG. 3, the mounting of an individual interconnect 36 to the base 32 is illustrated. In FIG. 3, the alignment fixture 48 is not shown for illustrative purposes. The interconnect 36 includes the contact members 38 in patterns matching the patterns of the contact bumps 12 on the components 30A. In addition, the interconnect 36 includes patterns of conductors 56, and bonding pads 58, in electrical communication with the contact members 38. The bonding pads 58 can be formed on recessed surfaces 37 located along opposite edges of the interconnect 36. The base 32 also includes patterns of conductors 60 in electrical communication with the external contacts 34 on the base 32. Bond wires 62 can be bonded to the bonding pads 58 on the interconnect 36, and to the conductors 60 on the base 32 to establish electrical communication therebetween. The recessed surfaces 37 of the interconnect 36 allow the bond wires 62 to be attached with a minimum of interference with other system components. Electrical paths between the interconnect 36 and base 32 can also be formed by flex circuit (not shown) or mechanical electrical connectors such as clips or pins (not shown).

Referring to FIG. 3A, an individual contact member 38 is illustrated in greater detail. In the illustrative embodiment, each contact member 38 comprises an indentation 64 formed in a substrate 68 of the interconnect 36. Each indentation 64 is covered with a conductive layer 66 in electrical communication with a corresponding conductor 56 formed on a surface of the substrate 68. Each indentation 64 is sized to retain and electrically contact an individual contact bump 12. In addition, each indentation 64 can include sloped sidewalls for guiding and aligning the contact bumps 12.

The substrate 68 of the interconnect 36 can comprise ceramic, plastic, polyimide, FR-4, photo-machineable glass, or a semiconducting material, such as silicon. The indentations 64 for the contact members 38 can be formed by etching or machining the substrate 68. The conductive layer 66 and conductors 56 can be formed within the indentations 64, and on the surface of the substrate 68 out of highly conductive metals, such as aluminum, copper and tungsten, using a suitable metallization process (deposition, patterning, etching).

Referring to FIG. 4A, an alternate embodiment contact member 38S includes a stepped indentation 64S. The stepped indentation 64S can have a stepped-pyramidal, or inverted "ziggurat" shape, comprising an upper cavity with sloped walls, and a smaller lower cavity with sloped walls. Again the indentation 64S is covered by a conductive layer 66S in electrical communication with a corresponding conductor 56S. In this embodiment, the conductive layer 66S includes edges 70. The indentation 64S can be sized such that the edges 70 penetrate any oxide layers and electrically engage the contact bumps 12. As shown in FIG. 4B, because of size variations in the contact bumps 12 and large biasing forces, some contact bumps 12 may press into the lower cavity of the indentation 64S to form a deformed contact bump 12D. In this case the upper cavity of the indentation 64S limits further deformation of the contact bump 12.

Other types of contact members configured to make non-bonded, temporary electrical connections with contact bumps 12 are described in the following U.S. Patent Applications, which are incorporated herein by reference:

U.S. patent application Ser. No. 08/829,193, entitled "Interconnect Having Recessed Contact Members With Penetrating Blades For Testing Semiconductor Dice And Packages With Contact Bumps";

U.S. patent application Ser. No. 08/823,490, entitled "Method, Apparatus And System For Testing Bumped Semiconductor Components"; and

U.S. patent application Ser. No. 08/867,551, entitled "Interconnect For Making Temporary Electrical Connections With Bumped Semiconductor Components.

Referring to FIGS. 5 and 5A, a semiconductor component 30A configured for use with the test system 28 (FIG. 2A) is illustrated. The semiconductor component 30A comprises a semiconductor die (e.g., 10--FIG. 1A) or a chip scale package (e.g., 14A--FIG. 1B, 14B--FIG. 1C) with contact bumps 12 formed substantially as previously described. In addition, the component 30A includes an alignment member comprising a beveled edge 72A formed on the outer periphery of the component 30A along the face (circuit side) and edges thereof. As will be further explained, the beveled edge 72A can be configured to contact alignment surfaces on the alignment opening 50 (FIG. 2A) of the alignment fixture 48 (FIG. 2A), to guide and align the component 30A with respect to the interconnect 36 (FIG. 2A).

An angle of the beveled edge 72A can be selected as required (e.g., 30.degree., 45.degree., 60.degree.). In addition, the beveled edge 72 can be formed through a portion of a thickness of the component 30A as shown, or through a full thickness of the component 30A. One method for forming the beveled edge 72A comprises fabricating the component 30A on a wafer (not shown), and then sawing the wafer using a beveled saw blade. For example, the beveled edge 72A can be formed during a first saw cut with a beveled saw blade. During a second saw cut, a straight edged saw blade can be used to singulate the component 30A