A programmable logic device may include a programmable interconnect structure and a plurality of configurable logic elements including data latches interconnected by the interconnect structure. At least one of the configurable logic elements may be configurable as both a shift register and a lookup table. Also, the shift register may be enabled to operate as a bi-directional shift register by the inclusion of a first circuit for configuring the data latches either as series-connected inverters during a shift operation or as data latches after each shift operation. A second circuit for selecting a direction of shifting may also be included, as well as a third circuit for supplying data to the input of the shift register as determined by the direction of shifting.

In order to achieve rapid reconfiguration of logic elements in a programmable logic device, a plurality of memory logic modules are arranged in a two-dimensional array. At least one logic element is provided in each of the plurality of memory logic modules. The logic element is provided with a configuration memory into which configuration data can be written to specify logic functions of the logic element. A memory element is provided in each of the plurality of memory logic modules. The memory element stores a plurality of configuration data with respect to the logic element, and one of the plurality of configuration data is written into the configuration memory of the logic element to configure or reconfigure the logic element.

A new digital configurable macro architecture is described. The digital configurable macro architecture is well suited for microcontroller or controller designs. In particular, the foundation of the digital configurable macro architecture is a programmable digital circuit block. The programmable digital circuit blocks can be configured to coupled in series or in parallel to handle more complex digital functions. More importantly, the configuration of the programmable digital circuit block is determined by its small number of configuration registers. This provides much flexibility. In particular, the configuration of the programmable digital circuit block is fast and easy since changes in configuration are accomplished by changing the contents of the configuration registers, whereas the contents are generally a small number of configuration data bits. Thus, the programmable digital circuit block is dynamically configurable from one predetermined digital function to another predetermined digital function for real-time processing.

A configuration state memory is associated with a configurable functional block on a reconfigurable chip. The configuration state memory stores more than one configuration for the functional block. This allows the functional block to switch configurations without requiring the configuration data to be loaded from off-chip which would stall the operation of the reconfigurable chip. In a preferred embodiment, the configuration state memory uses a relatively few address bits to produce a relatively broad configuration output to the functional blocks. The small number of input address bits allows the configuration state memory to be addressed by relatively small state machine unit.

A microcontroller with a mixed analog/digital architecture including multiple digital programmable blocks and multiple analog programmable blocks in a communication array having a programmable interconnect structure. The single chip design is implemented by integration of programmable digital and analog circuit blocks that are able to communicate with each other. Robust analog and digital blocks that are flash memory programmable can be utilized to realize complex design applications that otherwise would require multiple chips and/or separate applications. The programmable chip architecture includes a novel array having programmable digital blocks that can communicate with programmable analog blocks using a programmable interconnect structure. The programmable analog array contains a complement of Continuous Time (CT) blocks and a complement of Switched Capacitor (SC) blocks that can communicate together. The analog blocks consist of multi-function circuits programmable for one or more different analog functions, and fixed function circuits programmable for a fixed function with variable parameters. The digital blocks include standard multi-function circuits and enhanced circuits having functions not included in the standard digital circuits. The programmable array is programmed by flash memory and programming allows dynamic reconfiguration. That is, "on-the-fly" reconfiguration of the programmable blocks is allowed. The programmable analog array with both Continuous Time analog blocks and Switched Capacitor analog blocks are offered on a single chip along with programmable digital blocks. The programmable interconnect structure provides for communication of input/output data between all analog and digital blocks.