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Claims  |
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I claim:
1. A semiconductor device, comprising:
a plurality of primary and redundant circuit elements, the plurality of primary circuit elements being addressable by electrically conductive row and column lines based on an external address word having a predetermined bit length, the plurality
of primary and redundant circuit elements being divided into at least first and second sets wherein primary and redundant circuit elements in the first and second sets are not simultaneously active, wherein the first and second sets of redundant circuit
elements can substitute for defective circuit elements in the first and second sets of primary circuit elements, respectively, and wherein the redundant circuit elements are divided into at least a plurality of columns;
control and addressing circuitry coupled to the electrically conductive row and column lines for permitting communication with the plurality of primary circuit elements based on the external address word supplied thereto;
at least first and second sets of fuse banks for storing addresses of defective circuit elements in the first and second sets of primary circuit elements, respectively; and
a number of electrically conductive intercoupling lines equal to a number of columns of redundant circuit elements in the first set of redundant circuit elements, the intercoupling lines being coupled to the first and second sets of fuse banks
and to both the first and second sets of redundant circuit elements, and wherein the intercoupling lines are shared by the first and second sets of fuse banks and by first and second sets of redundant elements as the first and second sets of redundant
elements are not simultaneously active.
2. The semiconductor device of claim 1, further comprising:
a plurality of sense amplifiers coupled to and shared between the first and second sets of circuit elements;
a plurality of isolation gates coupled between the first and second sets of circuit elements and the shared sense amplifiers, the isolation gates disabling either the first or second set of circuit elements when the second or first set of circuit
elements, respectively, is actively coupled to at least one of the plurality of shared sense amplifiers so that circuit elements in the first and second sets are not simultaneously active.
3. The semiconductor device of claim 1, further comprising:
at least one comparison circuit coupled to the control and addressing circuitry and the match lines, the comparison circuit comparing the external address word to the stored addresses in either the first or second fuse banks and outputting a
match signal, on one of the lines, to access one of the columns of redundant circuit elements if the address word and one of the stored addresses correlate; and
at least one multiplexing circuit coupled between the comparison circuit and the first and second fuse banks, the multiplexing circuit receiving at least one bit of the address word and selecting, based thereon, one of the first and second fuse
banks to couple to the comparison circuit.
4. The semiconductor device of claim 1 wherein the redundant circuit elements are divided into a plurality of rows and the plurality of columns, wherein a number of fuse banks in the first and second sets of fuse banks equals a number of
redundant rows and columns, and wherein the circuit elements are memory cells.
5. The semiconductor device of claim 1, further comprising a plurality of multiplexing circuits coupled to the first and second fuse banks and a plurality of comparison circuits, wherein the redundant circuit elements are divided into a
plurality of rows and the plurality of columns,
wherein a first two of every four fuse banks provide addresses corresponding to redundant rows and columns in the first set and a second two of every four fuse banks provide addresses corresponding to redundant rows and columns in the second set,
wherein a first multiplexing circuit is coupled to the first two of every four fuse banks, a second multiplexing circuit is coupled to the second two of every four fuse banks, and a third multiplexing circuit is coupled to the first and second
multiplexing circuits,
wherein each of the third multiplexing circuits is coupled to one of the plurality of comparison circuits, and
wherein each of the comparison circuits is coupled to one of the match lines.
6. The semiconductor device of claim 1, further comprising a plurality of row and column decoders coupled to the first and second sets of circuit elements, and wherein the match lines are coupled to each of the row and column decoders.
7. In a semiconductor device having a plurality of primary circuit elements addressable based on an external address word, and a plurality of redundant circuit elements, wherein some of the primary elements can be defective, a method of
accessing one of the redundant memory elements comprising:
dividing the plurality of primary and redundant circuit elements into first and second planes that are not simultaneously active;
storing at least two sets of addresses of defective circuit elements in the plurality of primary circuit elements;
receiving the external address word;
selecting one of the sets of stored addresses based on the received external address word and based on which of the first and second planes are active;
retrieving a stored address in the selected set of stored addresses;
comparing the retrieved stored address to the external address word; and
accessing one of the redundant memory elements based on the comparing.
8. The method of claim 7 wherein receiving the external address word includes decoding the external address word, and wherein selecting includes selecting one of the sets of stored addresses based on one bit in the decoded address.
9. The method of claim 7 wherein selecting includes multiplexing between the sets of stored addresses.
10. A computer system comprising:
an input device;
an output device;
an address bus;
a data bus;
a set of control lines;
a memory controller coupled to the address and data buses and to the set of control lines;
a processor coupled to the input and output devices, to the address and data buses and to the set of control lines; and
a memory device coupled to the memory controller through the address and data buses and the set of control lines, the memory device comprising:
a plurality of primary and redundant memory elements, the plurality of primary memory elements being addressable by electrically conductive row and column lines based on an external address word having a predetermined bit length, the plurality of
primary and redundant memory elements being divided into at least first and second sets, wherein primary and redundant memory elements in the first and second sits are not simultaneously active, wherein the first and second sets of redundant memory
elements can substitute for defective memory elements in the first and second sets of primary memory elements, respectively, and wherein the redundant memory elements are divided into at least a plurality of columns;
control and addressing circuitry coupled to the electrically conductive row and column lines for permitting communication with the plurality of primary memory elements based on the external address word supplied thereto;
at least first and second sets of fuse banks for storing addresses of defective memory elements in the first and second sets of primary memory elements, respectively; and
a number of electrically conductive intercoupling lines equal to a number of columns of redundant memory elements in the first set of redundant memory elements, the intercoupling lines being coupled to the first and second sets of fuse banks and
to both the first and second sets of redundant memory elements, and wherein the intercoupling lines are shared by the first and second sets of fuse banks and by the first and second sets of redundant memory elements as the first and second sets of
redundant elements are not simultaneously active.
11. The computer system of claim 10, further comprising:
a plurality of sense amplifiers coupled to and shared between the first and second sets of memory elements;
a plurality of isolation gates coupled between the first and second sets of memory elements and the shared sense amplifiers, the isolation gates disabling either the first or second set of memory elements when the second or first set of memory
elements, respectively, is actively coupled to at least one of the plurality of shared sense amplifiers so that memory elements in the first and second sets are not simultaneously active.
12. The computer system of claim 10, further comprising:
at least one comparison circuit coupled to the control and addressing circuitry and the match lines, the comparison circuit comparing the external address word to the stored addresses in either the first or second fuse banks and outputting a
match signal, on one of the lines, to access one of the columns of redundant memory elements if the address word and one of the stored addresses correlate; and
at least one multiplexing circuit coupled between the comparison circuit and the first and second fuse banks, the multiplexing circuit receiving at least one bit of the address word and selecting, based thereon, one of the first and second fuse
banks to couple to the comparison circuit.
13. The computer system of claim 10 wherein the redundant memory elements are divided into a plurality of rows and the plurality of columns, wherein a number of fuse banks in the first and second sets of fuse banks equals a number of redundant
rows and columns.
14. The computer system of claim 10, further comprising a plurality of row and column decoders coupled to the first and second sets of memory elements, and wherein the match lines are coupled to each of the row and column decoders.
15. In a semiconductor memory device having a plurality of primary memory elements, and a plurality of redundant memory elements, wherein some of the primary memory elements can be defective, a method of accessing one of the redundant memory
elements comprising:
dividing the plurality of primary and redundant memory elements into first and second planes that are not simultaneously active;
selecting one of at least two the sets of stored addresses based on a received external address word to the semiconductor memory device and based on which of the first and second planes are active;
comparing a stored address to an externally received address word; and
employing one of the redundant memory elements based on the comparing.
16. The method of claim 15, further comprising decoding the external address word, and wherein the selecting includes selects one of the sets of stored addresses based on one bit in the decoded address.
17. The method of claim 15 wherein selecting includes switching between the sets of stored addresses.
18. A semiconductor device, comprising:
a plurality of primary circuit elements, addressable by electrically conductive row and column lines based on an external address word having a predetermined bit length, the plurality of primary circuit elements being divided into a plurality of
sets wherein when circuit elements in one of the sets are active, circuit elements in the other sets are not active;
a plurality of sets of redundant circuit elements, substitutable for defective circuit elements in the sets of primary circuit elements, wherein the plurality of redundant circuit elements are divided into at least a plurality of columns, wherein
when redundant circuit elements in one of the sets are active, redundant circuit elements in the other sets are not active;
circuitry coupled to the electrically conductive row and column lines for permitting communication with the plurality of primary circuit elements based on the external address word supplied thereto;
a plurality of storage banks for storing addresses of defective circuit elements in the sets of primary circuit elements; and
a number of electrically conductive intercoupling lines equal to only a number of columns of redundant circuit elements in one of the sets of redundant circuit elements, the intercoupling lines being coupled to the plurality of storage banks and
to the sets of redundant circuit elements, and wherein the intercoupling lines are shared by the plurality of storage banks and by the sets of redundant circuit elements as the circuit elements in one of the sets are active, while the circuit elements in
the other sets are not active.
19. The semiconductor device of claim 18, further comprising:
a plurality of amplifiers coupled to and shared between the sets of circuit elements; and
a plurality of gates coupled between the sets of circuit elements and the shared amplifiers, the gates disabling all but one of the sets of circuit elements.
20. The semiconductor device of claim 18, further comprising:
at least one comparison circuit coupled to the circuitry and the match lines, the comparison circuit comparing the external address word to the stored addresses in one of the storage banks and outputting a match signal, on one of the lines, to
access one of the columns of redundant circuit elements if the address word and one of the stored addresses correlate; and
at least one switch circuit coupled between the comparison circuit and the storage banks, the switch circuit receiving at least one bit of the address word and selecting, based thereon, one of the storage banks to couple to the comparison
circuit.
21. The semiconductor device of claim 18 wherein the redundant circuit elements are divided into a plurality of rows and the plurality of columns, wherein a number of storage banks in the sets of storage banks equals a number of redundant rows
and columns.
22. The semiconductor device of claim 18, further comprising a plurality of row and column decoders coupled to the sets of circuit elements, and wherein the match lines are coupled to each of the row and column decoders . |
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Description |
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TECHNICAL FIELD
The present invention relates to an apparatus and method for testing semiconductor electrical devices, particularly memory devices.
BACKGROUND OF THE INVENTION
Testing is performed on semiconductor devices to locate defeats and failures in such devices, typically occurring during the manufacture of the semiconductor devices. As circuit density on semiconductor devices increases, the number of defects
and failures can increase. Semiconductor manufacturers, therefore, have an increasing need to detect defects and failures in semiconductor devices as circuit density increases.
Thus, for quality control of semiconductor devices, semiconductor devices are tested, often before a die containing the semiconductor device is packaged into a chip. A series of probes on a test station electrically contact pads on each die in a
wafer to access portions of the individual semiconductor devices on the die. For example, in a semiconductor memory device, the probes contact address pads and data input/output pads to access selected memory cells in the memory device. Typical dynamic
random access memory devices ("DRAM") include one or more arrays of memory cells that are each arranged in rows and columns. Each array of memory cells includes word or row lines that select memory cells along a selected row, and bit or column lines (or
pairs of lines) that select individual memory cells along a row to read data from, or write data to, the cells in the selected row.
During testing, predetermined data values are typically written to selected row and column addresses that correspond to certain memory cells, and then the voltage values are read from those memory cells to determine if the data read matches the
data written to those addresses. If the read data does not match the written data, then the memory cells at the selected addresses likely contain defects and the semiconductor device fails the test.
Nearly all semiconductor devices, particularly memory devices, include redundant circuitry on the semiconductor device that can be employed to replace malfunctioning circuits found during testing. By enabling such redundant circuitry, the device
need not be discarded even if it fails a particular test. For example, memory devices typically employ redundant rows and columns of memory cells so that if a memory cell in a column or row of the primary memory array is defective, then an entire column
or row of redundant memory cells can be substituted therefor, respectively.
Substitution of one of the spare rows or columns is conventionally accomplished by opening a specific combination of fuses (or closing antifuses) in one of several fuse banks on the die. Conventional fuses include polysilicon fuses which can be
opened by a laser beam, and also avalanche-type fuses and antifuses. If a given row or column in the array contains a defective memory cell, then the wafer can be moved to another station where a laser blows a fuse to enable a redundant row or column.
The laser blows a selected combination of fuses to provide an address equal to the address of the defective cell. For example, if the defective cell has an eight-bit binary address of 11011011, then the laser blows the third and sixth fuses in a
set of eight fuses within one of several fuse banks, thereby storing this address. A compare circuit compares each incoming address to the blown fuse addresses stored in the fuse banks to determine whether the incoming address matches with one of the
blown fuse addresses. If the compare circuit determines a match, then it outputs a match signal (typically one bit) to a controller or "phase generator" in a row or column decoder for the memory device. In response thereto, the row or column decoder
causes the appropriate redundant row/column to be accessed for data transfer, and ignores the defective row or column in the primary memory array.
The rows and columns of redundant memory cells necessarily occupy space on the die. Moreover, the compare circuitry necessary for accessing the redundant row or column requires space on the die. Compare circuits typically employ multiple
exclusive OR gates which require a greater amount of area than other logic gates such as NAND and NOR gates. At least one compare circuit is required for each bank of fuses.
Furthermore, fuses/antifuses and compare circuits are typically located at the periphery of the primary memory array. As a result, lines must be routed from the compare circuits to the redundant row; and columns. These additional lines further
take up area on the die. If the compare circuits and fuses were located adjacent to their respective redundant rows or columns, the complexity of the layout of the memory device will increase, which is undesirable.
Semiconductor circuit designers strive to provide greater circuit density on a die of a given size. The die size is typically a size standardized by the semiconductor industry. By providing additional circuitry on a given die, the product
incorporating the die is able to provide enhanced or superior performance over competing products in the marketplace. Therefore, there is a need to reduce the area on the die required for redundant rows and columns.
Semiconductor circuit designers have attempted to reduce the number of redundant rows and columns (and their associated circuitry and lines), and thereby free up precious area on the die for additional circuitry to enhance the performance or
functionality of the circuitry on the die. However, by so reducing the number of redundant rows and columns, an insufficient number of redundant rows and columns may exist, so that the entire die must be discarded.
An additional problem with reducing the number of redundant memory elements relates to dividing the primary memory array into sub-arrays. Current memory devices divide the primary array of memory cells into sub-arrays so that only a portion of
the memory need be energized in a given access, resulting in significant power reduction. Each sub-array requires its own redundant rows and columns. By dividing the memory array into two sub-arrays or "planes," the redundant rows and columns in the
first plane can be substituted for any defective row or column in the primary rows/columns of memory cells in the first plane. Although the memory array could be further divided into a greater number of planes (e.g., four) to further reduce power
consumption, then an even fewer number of redundant rows and columns can be employed to replace defective rows and columns in one-fourth of the primary memory array. If a greater number of errors occurred within one quarter of the memory array, then an
insufficient number of redundant rows/columns will be available to compensate for such defects. Alternatively, no planes could be employed so that all of the redundant rows and columns can be used to replace defective rows and columns throughout the
memory anywhere throughout the memory array. However, such a scheme requires a greater number of routing lines as compared to dividing the array into two planes.
One known 1-megabit.times.4 DRAM device, manufactured by Micron Technology, employs a 2:1 multiplexer to selectively couple a row address fuse bank and a column address fuse bank with one compare circuit. Row addresses and column addresses are
typically compared by compare circuits to column and row fuse addresses at different times during read/write cycles in a semiconductor memory device. As a result, at no time will the compare circuit be required to compare an address to both a column
address stored in one fuse bank and a row address stored in another fuse bank. Consequently, this known 1-megabit.times.4 DRAM device employs one compare circuit for every two fuse banks by employing a 2:1 multiplexer. Since 2:1 multiplexers employ, at
a minimum, two pass gates, while compare circuits employ exclusive OR gates, 2:1 multiplexers require substantially less die area than compare circuits. Therefore, by reducing the number of compare circuits, this prior 1-megabit.times.4. DRAM device
reduces the area on a die. However, there is still a need to further reduce the area on the die.
Semiconductor circuit designers have attempted to reduce the overall number of redundant rows/columns to thereby increase die area by experimenting with improved manufacturing techniques to reduce the number of defects on such dies, to thereby
afford them the ability to reduce the number of redundant rows and columns necessary to compensate for defects. However, as circuit densities increase, defects tend to increase, despite the best improvements in manufacturing techniques.
SUMMARY OF THE INVENTION
The present invention further reduces the area on a die required for rows and columns of redundant memory cells by sharing compare circuitry with banks of redundant memory cells based on division of the primary memory array into two or more
"planes." Pass gates or multiplexers coupled between at least two banks of fuses and one compare circuit selectively couple the appropriate fuse bank to the compare circuit. Preferably, a bit in the address (e.g., address bit RA9 in a row address word
having address bits A0-A10) is received by and controls the multiplexer to select between the two banks of fuses. As a result, only one compare circuit is required for two fuse banks for a redundant row and a redundant column, and also for a pair of
redundant row and columns for each plane.
Additionally, the present invention reduces the number of lines coupled between the compare circuits and the rows and columns of redundant memory elements in the memory array. The present invention maps or assigns groups or planes of memory
elements into preferably one of two planes. The planes span between blocks of memory in the memory array, where each block is divided by shared sense amplifiers. As a result, while eight lines are coupled to 16 rows or columns, only eight rows or
columns will be active at any one time because isolation gates will enable only eight of the 16 rows or columns within two planes of memory. Consequently, the present invention saves on the number of lines required to intercouple the compare circuits to
the redundant rows/columns, thereby realizing increased area on the chip for additional circuitry. Additionally, at no time will both blocks of memory on opposite sides of the shared sense amplifier ever be simultaneously energized. Even with the most
compressed address testing, no rows or columns on opposite sides of shared sense amplifiers will be energized. Therefore, the layout of memory cells under the present invention will not interfere with even the most compressed address mode testing of the
semiconductor memory device.
In a broad sense, the present invention embodies a semiconductor device having a plurality of primary and redundant circuit: elements, control and addressing circuitry, at least first and second sets of fuse hanks, and a number of electrically
conductive intercoupling lines. The plurality of primary circuit elements are addressable by electrically conductive row and column lines based on an external address word having a predetermined bit length. The plurality of primary and redundant
circuit elements are divided into at least first and second sets, wherein circuit elements in the first and second sets are not simultaneously active. The first set of redundant elements can substitute for defective circuit elements in the first set of
primary circuit elements, and the second set of redundant circuit elements can substitute for defective circuit elements in the second set of primary circuit elements. The redundant circuit elements are divided into at least a plurality of columns.
The control and addressing circuitry is coupled to the electrically conductive row and column lines and permits communication with a plurality of primary circuit elements based on the external address word supplied thereto. The first and second
sets of fuse banks store addresses of defective circuit elements in the first and second sets of primary circuit elements, respectively. The number of electrically conductive intercoupling lines is equal to a number of columns of redundant circuit
elements in the first set of redundant circuit elements. The intercoupling lines are coupled to the first and second sets of fuse banks and to both the first and second sets of redundant circuit elements.
The present invention also embodies a semiconductor device including a plurality of primary and redundant circuit elements, control and addressing circuitry, at least first and second sets of fuse banks, at least one comparison circuit, and at
least one gating circuit. The plurality of primary circuit elements are addressable by electrically conductive row and column lines based on an external address word having a predetermined bit length. The plurality of primary and redundant circuit
elements are divided into at least first and second sets wherein circuit elements in the first and second sets are not simultaneously active. The first and second sets of redundant circuit elements an substitute for defective circuit elements in the
first and second sets of primary circuit elements, respectively. The redundant circuit elements are divided into at least a plurality of columns.
The control and addressing circuitry is coupled to the electrically conductive row and column lines, and permit communication with the plurality of primary circuit elements based on the external address word supplied thereto. The first and
second sets of fuse banks store addresses of defective circuit elements in the first and second sets of primary circuit elements, respectively. The comparison circuit is coupled to the control and addressing circuit and to the first and second sets of
circuit elements. The comparison circuit compares the external address word to the stored addresses in either the first or second fuse banks, and outputs a match signal to access one of the columns of redundant circuit elements if the address word and
one of the stored addresses correlate. The gating or multiplexing circuit is coupled between the comparison circuit and the first and second fuse banks. The gating circuit receives at least one bit of the address word and selects, based thereon, one of
the first and second fuse banks to couple to the comparison circuit.
The present invention solves problems inherent in the prior art of semiconductor devices by increasing realized substrate area on a die by employing multiplexers or selection circuits to allow at least four banks of fuses to share one compare
circuit. Additionally, to further realize increased area savings on the substrate, the memory array is divided into planes separated by shared sense amplifiers so that a number n of lines can be routed from the compare circuits to at least 2.times.n
number of redundant rows/columns, but where only n number of rows/columns are active at any one time due to appropriate selection by isolation gates in the semiconductor device. Other features and advantages of the present invention will become apparent
from studying the following detailed description of the presently preferred embodiment, together with the following drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a semiconductor memory device under the present invention.
FIGS. 2A and 2B together form a block diagram of the memory array, fuse banks and compare circuitry of the semiconductor memory device of FIG. 1.
FIG. 3 is an enlarged block diagram of FIGS. 2A and 2B showing four blocks of memory cells, compare circuits, multiplexers, fuse banks, and other associated circuitry for the semiconductor memory device of FIG. 1.
FIG. 4 is a block diagram of several blocks of memory, and fuse banks, multiplexers and compare circuits for the semiconductor memory device of FIG. 1.
FIG. 5 is a block diagram of the fuse banks and compare circuits of a portion of FIG. 4.
FIG. 6 is a partial schematic, partial block diagram of one of the compare circuits of FIG. 4.
FIG. 7 is a block diagram of a computer system that incorporates the memory device of FIG. 1.
DETAILED DESCRIPTION OF THE INVENTION
Referring to FIG. 1, a memory device 100 includes one or more memory arrays 102 each having primary memory sub-arrays such as two sub-arrays 103 and 105. Each of the primary memory sub-arrays 103 and 105 has redundant rows 107 and redundant
columns 108 of memory cells. As described above, the redundant rows and columns 107 and 108 are selectively enabled to replace defective rows or columns of memory cells, respectively, in the primary memory sub-arrays 103 and 105.
Control logic and address buffer circuitry 110 receives externally applied signals such as an 11-bit addresses word on address lines or pins A0-A10. The control logic and address buffer circuitry 110 also receives externally generated control
signals such as column address strobe CAS, row address strobe RAS, write enable WE, and so forth, as is known by those skilled in the relevant art. When the control logic and address buffer circuitry 110 receives the addresses on address lines A0-A10,
it buffers and latches the addresses, and outputs them to one or more row decoders 111 and column decoders 112. If, for example, the memory array 102 is a 2 megabit by 8 array, then the row decoders 111 typically decode the higher order bits of the
external address A0-A10 into an 11 bit row address RA0-RA10, while the column decoders 112 decode the lower order bits into an 11 bit column address CA0-CA10. The row decoders 111 apply the decoded address to the memory array 102 to enable a selected
row in the array, while the column decoders 112, through sense amplifiers 114 and input/output gating circuits 115, employ the decoded column address to enable one or more columns in the memory array. The sense amplifiers 114 sense a value on the one or
more columns and outputs the data to data input/output buffers 116, which in turn provide the data to data lines.
While the sense amplifiers 114 and input/output gating circuits 115 are shown as separate from the memory array 102, the sense amplifiers 114 and input/output gating circuits 115 are typically formed between blocks of memory within the memory
array 102, as described more fully below. Sense amplifiers typically occupy relatively large area on the die, and therefore sense amplifiers are typically shared between at least two columns. For example, as explained below, each of the sub-arrays 103
and 105 of the memory array 102 is divided into multiple blocks of memory cells, where pairs of blocks are connected to the same group of sense amplifiers 114.
To isolate one column in one block of memory from the sense amplifier 114 when reading from the other column in the ether block of memory, an isolation gate, typically a transistor, within the input/output gating circuit 115 is employed between
the two columns. Thus, to isolate one column in one memory block from another column, the corresponding isolation transistor is turned off to disconnect the first column from the shared sense amplifier. Similarly, for the other column to be accessed,
the corresponding isolation transistor is turned on, while the other isolation transistor coupled to the first column is turned off. In operation, two blocks of memory, sharing common sense amplifiers, are never simultaneously energized. Therefore, the
sense amplifiers for one block isolate, and therefore de-energize, one block of memory cells from the other.
The memory device 100 also includes compare circuitry and fuse banks 120 shown as part of the control logic and address buffer circuitry 110, and as described more fully below. The control logic and address buffer circuitry 110, in response to
the CAS, RAS, WE, and other control signals, operates the row decoders 111, column decoders 112, sense amps 114, I/O gating circuits 115, and data I/O buffers 116 to write data to, or read data from, the array 102. Additional description regarding
writing data to, or reading data from, the memory device 100 is unnecessary, as such details are known to those skilled in the art.
Referring to FIGS. 2A and 2B, an exemplary layout for the memory array 102 is shown as dividing the sub-arrays 103 and 105 into eight one-megabit sections 300-307. A first higher order subgroup 310 includes sections 300 and 301, while a first
lower order subgroup 311 includes sections 302 and 303. A second higher order subgroup 312 includes sections 304 and 305, while a second lower order subgroup 313 includes sections 306 and 307. A group of higher order sections 314 includes subgroups 310
and 311, while a group of lower order sections includes subgroups 312 and 313.
Each of the sections 300-307 is divided into 256K blocks of memory cells 201-264, for a total of 64 such blocks. The column decoders 112, and redundant rows of memory cells 107, are positioned between blocks of memory cells within each section
300-307. Each block of memory cells 201-264 includes portions of one or more columns of redundant memory cells 108, as explained below. The fuse banks and compare circuitry 120 are shown at one end of the sub-arrays 103 and 105, and are coupled to each
of the blocks of memory cells by means of eight lines 138 running between the sub-arrays.
In the 11-bit decoded row address, the nine least significant bits RA0-RA8 identify a row within the blocks of memory cells 201-264. The most significant bit in the column address, CA10, selects between the group of lower order sections 314
(including sections 300, 301, 302 and 303) and the group of higher order of sections 315 (including sections 304, 305, 306 and 307). Within each group of the lower and higher order sections 314 and 315, the most significant bit in the row address bit,
RA10, selects between the first and second lower and higher order subgroups 310 or 311 (which include sections 300 and 301, and 302 and 303, respectively), and subgroups 312 or 313 (which include sections 304 and 305, and 306 and 307, respectively). The
second most significant row address bit, RA9, then selects one of two sections within the selected lower or higher order subgroup 310, 311, 312 or 313.
Since the exemplary memory array 102 is 2-megabit by 8 memory array, an eight bit word is output for each externally applied address A0-A10, and thus two rows are simultaneously activated based on the word. For example, if a logical high value
corresponds to a higher order address, then to select a row within the blocks of memory cells 215, 231, 247, 263, and a row in the blocks 216, 232, 248 and 264, the most significant column address bit, CA10, must first have a high value to select the
group of higher order sections 315. The most significant row address bit, A10, must have a high value to select the higher order subgroup 313, while the second most significant row address bit, A9, must have a high value to select section 307. The
remaining row address bits, RA0-RA8, then select the particular rows within the blocks of memory cells 215, 231, 247 and 263, and 216, 232, 248 and 264.
Similarly, to select four columns within the blocks of memory cells in section 307, the second most significant column address bit, CA9, selects between a group of lower order columns 320 and a group of higher order columns 322. Both of the
lower and higher order groups of columns 320 and 322 span the two subarrays 301 and 305, as shown in FIGS. 2A and 2B. In the exemplary memory array 102, both the lower and higher order column groups 320 and 322 are simultaneously powered up, and each
group activates, two columns for a given externally applied address. In other words, for each external address applied to the memory array 102, four bits are output by the lower order column section 320, while four bits are also output from the higher
order column section 322. Therefore, in the above example, one bit is output from each of the blocks of memory cells 215, 216, 231, 232, 247, 248, 263 and 264 based on the external address.
The memory array 102, as shown in FIGS. 2A and 2B, has row decoders 111 associated with each block of memory cells because the memory array is preferably fabricated with only a single layer of metal interconnect lines. Each of the multiple row
decoders 111 receives external addresses applied to an address bus (not shown) in the device 100. If the memory array 102 included two or more layers of metalizing interconnect layers, then a single, centrally located, row decoder could be employed.
The exemplary memory array 102, being a 2-megabit by 8 memory array, includes 16 columns of redundant memory cells 108, and 16 rows of redundant memory cells 107. Importantly, the blocks of memory cells within the memory cell array 102 are
divided into two sets or planes, plane A and plane B, based on the sections 300-307, where each plane has one-half of the total number of memory cells (i.e., each having 8 megabits). The rows and columns of redundant memory cells 107 and 108 are
similarly divided with eight redundant rows and columns for each plane A and B. Eight redundant rows/columns 107 and 108 can replace any defective row or column in the plane A of primary memory, while eight redundant rows/columns can replace any
defective row/column in plane B of the primary memory. It has been statistically found that eight redundant rows and columns for each 8-megabit plane is sufficient to replace the number of malfunctioning memory elements typically found during testing.
Rather than dividing the planes A and B based on the sub-arrays 103 and 105, the planes A and B span the two sub-arrays, as shows in FIGS. 2A and 2B. As explained more fully below, such a division of the memory array 102 allows for a reduced
number of lines intercoupling the row and column decoders 111 and 112 with the fuse banks and compare circuitry 120. The second most significant bit in the eleven bit row address (i.e., RA9) selects between the planes A and B. Therefore, for example.
if the row address bit RA9 has a high value, then sections 301, 303, 305 and 307 are enabled for plane A, while if the bit RA9 has a low value, then sections 300, 302, 304 and 306 are enabled for plane B. The row and column decoders 111 and 112 receive
this address bit (as well as the other address bits in the address word) to enable only at most half of the memory cells in the memory array 102 (i.e., either plane A or plane B). In other words, the planes A and B are logically separated by the row
address, namely the second most significant bit in the address.
While being spatially divided between various blocks, groups and sub-arrays of memory cells within the memory array 102, each of the redundant rows and columns are logically contiguous. For example, each of the eight redundant columns from plane
A physically extends through the blocks of memory cells 219, 220, 223, 224, 227, 228, 231, 232, 235, 236, 239, 240, 243, 244, 247 and 248, or through the blocks of memory cells 203, 204, 207, 208, 211, 212, 215, 216, 251, 252, 255, 256, 259, 260, 263 and
264, all of which are in plane A. The rows and columns of redundant cells 107 and 108 in plane A do not extend through the blocks of memory cells within the plane B. Likewise, a logically contiguous row or column of redundant cells 107 or 108 in plane B
physically extends through all blocks of memory cells in plane B, but none of the memory cells in plane A.
As shown more clearly in FIG. 3, the planes A and B are divided based on shared sense amplifiers 114 located between two blocks of memory cells. For example, in the sub-array 103, the block 231 of memory cells forms part of plane A, while block
230 forms part of plane B. The blocks 231 and 230 are separated by shared sense amplifiers 114 (n channel sense amps) formed therebetween. Isolation gates 115A isolate the block of memory cells 231 from the shared sense amplifiers 114, while isolation
gates 115B isolate the block of memory cells 230 from the sense amplifiers. Similarly. in tie sub-array 105, the block 247 of memory cells forms part of the redundancy plane A, while the block 246 forms part of the redundancy plane B. The blocks 247'
and 246' are separated by shared sense amplifiers 114' formed therebetween. Isolation amplifiers 115A' isolate the block of memory cells 247 from the shared sense amplifiers 114', while isolation gates 115B' isolate the block of memory cells 246 from
the sense amplifiers.
Two sets of fuse banks 140 and 142 include several groups of fuses that can be selectively configured to permanently store addresses of defective memory cells within a row or column in the array of primary memory cells. The first set of fuse
banks 140 provides addresses for defective memory cells within the plane A of memory cells, while the second set of fuse banks 142 provides addresses for defective memory cells within the plane B of memory cells. As explained more fully below, several
two-to-one multiplexers 144 and 145 selectively couple the first or second sets of fuse banks 140 and 142 to several compare circuits 146. The compare circuits 146 receive external addresses from the control logic and address buffer circuitry 110 and
compare these addresses to addresses stored in one of the two sets of fuse banks 140 and 142.
In operation, if one or more rows of the primary memory cells contain defective cells therein, then the addresses for the defective cells are stored in the fuse banks 140 and 142 during initial testing of the device 100. The compare circuits 146
each receive an address from the control logic and address buffer circuitry 110 and compare it to one or more addresses stored in one of the first and second sets of fuse banks 140 and 142. The multiplexers 144 and 145 receive the second most
significant row address bit (e.g., RA9), which selects between the first and second sets of fuse banks 140 and 142, as explained more fully below. If the address received from the control logic and address buffer circuitry 110 matches one of the
addresses stored in the fuse banks 140 or 142, then the compare circuit 146 outputs a match signal M on one of the lines 138 to each of the row and column decoders 111 and 112.
If the device 100 is currently in its row access mode (e.g., after RAS falls), then the column decoders 112 ignore the signals on the lines 138, and only the row decoders 111 receive and decode the match signal M. If one of the eight lines 138
has a high value, then the row decoders 111 in response thereto enable the appropriate row of redundant memory cells in the redundant rows 107. For example, if one of the compare circuits 146 determines a match based on an incoming address, then it
outputs a match signal M on one of the lines 138 (e.g., on the first of eight lines). In response to this signal, each of the row decoders 111 enables one of the eight rows in the eight redundant rows 107 in the plane A (e.g., the first of eight
redundant rows).
Only eight lines 138 are employed to couple the compare circuits 146 with all of the redundant rows and columns 107 and 108 in the memory array 102. By dividing the planes along boundaries defined by the shared sense amplifiers 114, no two
redundant columns on either side of the shared sense amplifier will be simultaneously activated. In other words, no redundant columns 108 from plane B will be activated when redundant columns 108 from plane A are energized. Therefore, eight lines 138
can be coupled to eight redundant columns 108 running through the memory array 102, where the redundant columns can be conceptualized as having twice the length of standard columns in the array. The sense amplifiers 114 selectively enable only half of
the eight redundant columns at any one time. As a result, the eight redundant columns 107 are partitioned into two sets of eight columns each having standard length, thereby providing eight redundant columns for plane A and eight redundant columns for
plane B. Otherwise, as is currently performed in the art, at least 16 lines must be routed from the compare circuits 146 to 16 separate redundant rows and columns.
Referring to FIG. 4, the fuse banks 140, 142, multiplexers 144, 145 and compare circuits 146 are shown in greater detail. The first set of fuse banks 140 includes a first set of higher order fuse banks AR4, AC4, AR5, AC5, AR6, AC6, AR7, and AC7,
and a second set of lower order fuse banks AR0, AC0, AR1, AC1, AR2, AC2, AR3, and AC3, all for the plane A. Fuse banks AR0-AR7 correspond to the eight redundant rows of memory cells in the plane A, while the fuse banks AC0-AC7 correspond to the eight
redundant columns of memory cells in plane A.
Similarly, the second set of fuse banks 142 includes a first set of higher order fuse banks BR4, BC4, BR5, BC5, BR6, BC6, BR7, BC7, and a second set of lower order fuse banks BR0, BC0, BR1, BC1, BR2, BC2, BR3, and BC3. Fuse banks BR0-BR7
correspond to the eight redundant rows of memory elements in plane B while fuse banks BC0-BC7 correspond to the eight redundant columns of memory cells in plane B. Overall, there is a one-to-one correspondence between each fuse bank and each redundant
row or column so that each fuse bank is capable of causing only one row or column of redundant memory cells to be enabled, as described more fully below.
As shown in FIG. 4, each pair of fuse banks of a given order for redundant rows or columns. in a given redundancy plane, is coupled to a first set of 2:1 multiplexers 144. For example, the fifth order row and column fuse banks AR4 and AC4 in
the first set of fuse banks 140, are both coupled to the multiplexers 144. As is known in the art, an external address applied to the memory device 100 is broken up and decoded into separate row and column addresses. As a result, the external address
typically first enables a given row within the memory array 102, and thereafter, enables a specified column. The row and column addresses are never initially activated simultaneously to the memory array 102 (however, once the selected row is addressed,
it is held active until a given column is addressed). Therefore, as noted above, the row address can be compared to the row address stored in fuse bank AR4 at a first time (e.g., after RAS falls), while thereafter, the column address can be compared to
the address stored in the fuse bank AC4 at a second time (eg., after CAS falls). At no time will both of the row and column addresses be compared simultaneously. Therefore, the multiplexers 144 can selectively couple one of the two fuse banks AR4 and
AC4 to the output of the multiplexer depending upon whether an external row or column address is to be compared to a fuse row address or a fuse column address.
Likewise, only one of the two planes A or B of the memory array 102 will be energized based on a given address. Specifically, the second most significant bit in the 11-bit row address (bit RA9) is applied to a second set of 2:1 multiplexers 145
that select between the planes A and B. As noted above, if the second most significant address bit RA9 has a binary value of 0, then plane A is selected, while a binary value of 1 selects plane B. As a result, if plane A is selected, the compare circuits
146 need not compare an external address to fuse addresses in the second set of fuse banks 144 (i.e., addresses stored in fuse banks BR0-BR7 or BC0-BC7). Therefore, not only is one compare circuit 146 employed for each row and column fuse bank of a
particular order, but also row and column fuse banks of a particular order for both planes A and B are shared with the one compare circuit.
For example, fuse banks AR4 and AC4 are coupled to a multiplexer from the first set of multiplexers 144, fuse banks BR4 and BC4 are coupled to another multiplexer from the first set of multiplexers 144, and the two multiplexers 144 in turn are
coupled to a multiplexer from a second set of multiplexers 145 whose output is coupled to a single compare circuit 146. At a specific time during each read or write cycle for the memory device 100, the compare circuit 146 compares the external address
to one of the four fuse addresses stored in fuse banks AR4, AC4, BR4, BC4. Likewise, fuse banks AR5, AC5 are coupled to a multiplexer 144, fuse banks BR5 and BC5 are coupled to a multiplexer 144, and these two multiplexers are in turn coupled to a
multiplexer 145 whose output is coupled to another compare circuit 146. At a specific time during each read or write cycle, the compare circuit 146 compares the external address to one of the fuse addresses stored in fuse banks AR5, AC5, BR5 and BC5.
The remaining fuse banks in the first and second set of fuse banks 140 and 142 are likewise coupled to two multiplexers 144, one multiplier 145 and one compare circuit 146, | | |
