Stacked semiconductor package and method of fabrication

We claim:

1. A semiconductor package comprising:

a substrate comprising a plurality of first contacts on a first side thereof, a plurality of second contacts on an opposing second side thereof having a same pattern as the first contacts, a plurality of holes through the substrate at least partially filled with a conductive material electrically connecting the first contacts and the second contacts, a first cavity on the first side, a plurality of first pads within the first cavity in electrical communication with the first contacts, a second cavity on the second side, and an opening between the first cavity and the second cavity;

a semiconductor die in the second cavity comprising a plurality of second Dads aligned with the opening;

a plurality of wires extending through the opening and bonded to the first pads and the second Dads;

an encapsulant within the first cavity encapsulating the wires; and

a second substrate having a substantially same configuration as the substrate with a second semiconductor die mounted thereon, the second substrate stacked on the substrate with the second contacts on the second substrate bonded to the first contacts on the substrate.

2. The package of claim 1 wherein a death of the second cavity is approximately equal to a thickness of the semiconductor die.

3. The package of claim 1 wherein the first contacts comprise pads and the second contacts comprise metal bumps.

4. The package of claim 1 wherein the first contacts comprise pads and the second contacts comprise conductive elastomeric bumps.

5. The package of claim 1 wherein the substrate comprises a glass filled resin.

6. A semiconductor package comprising:

a first substrate comprising a plurality of conductors and first contacts on a first side thereof, a plurality of second contacts on an opposing second side thereof having a same pattern as the first contacts, a plurality of holes through the substrate at least partially filled with a conductive material electrically connecting the first contacts and the second contacts, a first cavity on the first side, a second cavity on the second side, and an opening between the first cavity and the second cavity;

a first semiconductor die in the second cavity comprising a plurality of bond pads aligned with the opening;

a plurality of electrical paths extending through the opening in electrical communication with the conductors and the bond pads;

an encapsulant within the first cavity substantially planar to the first side encapsulating the electrical paths; and

a second substrate and a second semiconductor die substantially identical to the first substrate and the first semiconductor die stacked on the first substrate with the second contacts on the second substrate bonded to the first contacts on the first substrate.

7. The package of claim 6 wherein the second contacts comprise solder bumps and the first contacts comprise solder wettable pads.

8. The package of claim 6 wherein the first contacts or the second contacts comprise a conductive elastomer.

9. The package of claim 6 wherein the conductive material comprises a metal or a conductive elastomer.

10. The package of claim 6 wherein the first substrate comprises a glass filled resin.

11. A semiconductor package comprising:

a panel comprising a plurality of substrates configured for separation into separate packages, each substrate comprising a plurality of conductors and first contacts on a first side thereof, a plurality of second contacts on an opposing second side thereof having a same pattern as the first contacts, a plurality of holes through the substrate at least partially filled with a conductive material electrically connecting the first contacts and the second contacts, a first cavity on the first side, a second cavity on the second side, and an opening between the first cavity and the second cavity;

a semiconductor die in the second cavity of each substrate;

a plurality of wires extending through the opening and bonded to the conductors and to the bond Dads of each substrate; and

an encapsulant within the first cavity encapsulating the wires of each substrate.

12. The package of claim 11 wherein the panel comprises a material selected from the group consisting of glass filled resin, silicon, ceramic, and plastic.

13. The package of claim 11 wherein the panel comprises a glass filled resin.

14. A semiconductor package comprising:

a first substrate comprising a first side and an opposing second side:

a first cavity in the first side;

a second cavity in the second side;

a plurality of first contacts on the first side in electrical communication with a plurality of first bond pads within the first cavity;

an opening in the substrate extending from the first cavity to the second cavity;

a first die in the second cavity comprising a plurality of second bond pads aligned with the opening;

a plurality of wires within the first cavity extending through the opening and bonded to the first bond pads and to the second bond pads;

an encapsulant within the first cavity substantially planar to the first side encapsulating the wires;

a plurality of second contacts on the second side;

a plurality of holes in the substrate at least partially filled with a conductive material electrically connecting the first contacts and the second contacts; and

a second substrate having a substantially same configuration as the first substrate and having a second die mounted thereto, the second substrate stacked on the first substrate with the second contacts thereon bonded to the first contacts on the first substrate.

15. The package of claim 14 wherein the second contacts comprise metal or conductive elastomeric bumps.

16. The package of claim 14 wherein the encapsulant comprises a material selected from the group consisting of epoxy, silicone, room temperature vulcanizing material, and polyimide.

17. The package of claim 14 wherein the second cavity has a depth substantially equal to a thickness of the first die.

18. The package of claim 14 wherein the first substrate comprises a plurality of separate layers laminated to form a unitary structure.

19. The package of claim 14 wherein the first substrate comprises a glass filled resin.

20. A semiconductor package comprising:

a substrate comprising a first side and an opposing second side;

a plurality of first contacts on the first sides

a first cavity on the first side;

a plurality of pads within the first cavity in electrical communication with the first contacts;

a die mounting cavity on the second side having a die mounted thereto;

an opening in the substrate extending from the first cavity to the die mounting cavity;

a plurality of electrical paths formed through the opening between the die and the pads;

a plurality of second contacts on the second side having a pattern substantially matching the first contacts;

a plurality of holes in the substrate at least partially filled with a conductive material electrically connecting the first contacts and the second contacts;

a planarized encapsulant within the first cavity encapsulating the electrical paths; and

a second substrate substantially identical to the substrate and having a second die mounted thereto, the second substrate stacked on the substrate with the second contacts thereon bonded to the first contacts on the substrate.

21. The package of claim 20 wherein the electrical paths comprise wire bonded wires.

22. The package of claim 20 wherein the electrical paths comprise solder.

23. The package of claim 20 wherein the second cavity has a depth substantially equal to a thickness of the first die.

Description Submit all comments and votes

FIELD OF THE INVENTION

This invention relates generally to semiconductor packaging. More particularly, this invention relates to an improved semiconductor package having a stacked configuration and containing multiple semiconductor dice, and to a method for fabricating the package.

BACKGROUND OF THE INVENTION

Semiconductor dice or chips are typically contained in semiconductor packages. This is sometimes referred to as the first level of packaging. The package is required to support, protect, and dissipate heat from a die, and to provide a lead system for power and signal distribution to the die. The package is also useful for performing burn-in and full functionality testing of the die.

In general, conventional plastic and ceramic packages incorporate several common elements. These common elements include a sealed package enclosure, a die attachment area, bond wires for establishing electrical communication with bond pads on the die, and a lead system for the package. One shortcoming of a conventional semiconductor package is that a peripheral outline (i.e., footprint) of the package is typically much larger than that of the die contained within the package (e.g., 10.times. or more). In addition, the manufacturing processes for conventional packages are relatively complicated, and require large capital expenditures.

Another type of package is referred to as a ball grid array (BGA) package. With this type of package, a substrate formed of a glass filled resin, or similar material, includes patterns of conductors in electrical communication with arrays of external contacts. One or more dice can be wire bonded to the conductors, and protected by a plastic material, such as a glob top encapsulant. A ball grid array package has a peripheral outline that is on the order of two to eight times that of the die. While the size is an improvement over conventional packages, this type of package also requires relatively complicated manufacturing processes, and has not received widespread acceptance in the industry.

Yet another type of package is referred to as a chip scale package. Typically, a chip scale package includes a substrate bonded to a face of a single die. The substrate includes external contacts for the package, such as solder balls in a ball grid array (BGA), or in a fine ball grid array (FBGA). The substrate for a chip scale package can comprise a flexible material, such as a polymer tape, or a rigid material, such as silicon, ceramic, or a glass filled resin. A chip scale package has a peripheral outline that is about the same as that of the die contained within the package (e.g., 1.2.times.). However, volume manufacture of chip scale packages has proven to be difficult. In particular forming reliable electrical connections between the die and substrate requires specialized equipment and techniques.

The present invention is directed to a semiconductor package that is simpler in construction, and cheaper to volume manufacture than any of the above conventional packages. In addition, the package has a relatively small peripheral outline, but is designed for fabrication in a stacked configuration, in which multiple dice can be contained in the same package.

SUMMARY OF THE INVENTION

In accordance with the present invention, a stacked semiconductor package, and a method for fabricating the package are provided. The package comprises a plurality of separate substrates, each having a semiconductor die mounted thereon, in electrical communication with external contacts and contact pads on opposing sides of the substrate. The substrates are configured for stacking to one another with the external contacts on a first substrate, bonded to the contact pads on an adjacent second substrate. In addition, the substrates are configured to provide a small outline package but with multiple semiconductor dice packaged in a high density configuration.

In an illustrative embodiment a first side of a substrate includes a wire bonding cavity having conductors in electrical communication with a pattern of contact pads A second side of the substrate includes a die mounting cavity, and a matching pattern of external contacts. An interconnect opening is formed through the substrate to provide access for wire bonding to bond pads on the die, and to the conductors on the first side of the substrate. In addition, an encapsulant can be formed within the wire bonding cavity to encapsulate and protect the wire bonds and associated wires. Preferably the encapsulant and the wire bonding cavity are configured to provide a planar surface to facilitate stacking of the substrate. In a similar manner, the die and the die mounting cavity can be configured to provide a planar surface for stacking of the substrate.

The substrate also includes interlevel conductors for electrically interconnecting the contact pads on the first side of the substrate to the external contacts on the second side of the substrate. The interlevel conductors comprise holes through the substrate and containing a metal, or a conductive elastomeric material.

The external contacts are configured for bonding to the contact pads of the adjacent stacked substrate. For example, the external contacts can be formed of a bondable material such as a solder, and the contact pads can be formed of a solder wettable material such as copper. Alternately, the external contacts can comprise a conductive elastomer deposited as a viscous paste, and then cured to form an electrically conductive bond with the contact pads. A conductive elastomer can also be placed between the external contacts and contact pads to form a conductive bond therebetween.

The method of fabrication can be performed using panels containing multiple substrates. Exemplary materials for fabricating the panels include glass filled resins, plastics, ceramic and silicon. Following fabrication of the panels, semiconductor dice can be adhesively bonded to the die mounting cavities on the first sides of the panels, and then wire bonded to the conductors on the second sides of the panels. Following encapsulation of the wire bonds, two or more panels can be stacked to one another, with the external contacts and contact pads on adjacent stacked panels in physical contact. Using a bonding process, such as a solder reflow, or a conductive elastomer curing process, the external contacts and contact pads on the adjacent stacked panels can then be bonded to one another. Following bonding, the stacked panels can be separated into separate packages using a cutting, shearing or breaking process.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic plan view of a panel suitable for fabricating semiconductor packages in accordance with the method of the invention;

FIGS. 2A-2D are schematic cross sectional views illustrating steps in the method of the invention;

FIG. 3 is a schematic plan view of a semiconductor package taken along section line 3--3 of FIG. 2C; and

FIG. 4 is a schematic bottom view of the semiconductor package taken along section line 4--4 of FIG. 2C.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1, a panel 10 includes a plurality of substrates 12 adapted to construct stacked semiconductor packages 14 (FIG. 2D) in accordance with the invention. In the illustrative embodiment the panel 10 contains thirty six substrates 12. However, the panel 10 can be formed with any convenient number of substrates 12. The substrates 12 can be formed on the panel using processes to be hereinafter described.

In the illustrative embodiment, the panel 10 comprises a glass filled resin such as an epoxy glass (FR-4), a polyimide glass or a cyanate-glass material. In addition to being electrically insulating and structurally rigid, these materials can be laminated, cured, and then metallized using deposition and photolithography processes. Also, required features can be punched or machined using processes employed in the fabrication of printed circuit boards (PCB), and other electronic devices.

Alternately, rather than the above materials, the panel 10 can comprise an electronics grade plastic, such as polyetherimide (PES), polyethersulfone (PES), polyether-ether ketone (PEEK), polyphenylene sulfide (PPS), or a liquid crystal polymer (LCP). With these plastics the panel 10 and substrates 12 can be shaped and metallized using a molding process such as 3-D injection molding.

Alternately, the panel 10 can comprise ceramic. With ceramic, a ceramic lamination and metallization process can be used to construct the panel 10 and substrates 12.

As another alternative, the panel 10 can comprise silicon, or other semiconducting material. With silicon, etching, micromachining, and metallization processes used for semiconductor circuit fabrication can be used to construct the panel 10 and substrates 12. One advantage of silicon is that a coefficient of thermal expansion (CTE) of the substrates 12 will exactly match the CTE of a silicon die.

The panel 10 can include boundary lines 16 for defining the peripheral outlines of the substrates 12. The boundary lines 16 can be configured to facilitate separation of the substrates 12 from the panel 10. For example, to facilitate separation, the boundary lines 16 can include perforations through the panel 10, similar to perforations for separating crackers. Alternately, the boundary lines 16 can be similar to scribe lines on semiconductor wafers, such as areas wherein the panel 10 is adapted to be cut, or sheared, using a suitable mechanism, such as a saw. The boundary lines 16 can also be omitted and the separation process used to define the peripheral outlines of the substrates 12.

Referring to FIGS. 2A-2D, steps in the method for fabricating the stacked semiconductor package 14 (FIG. 2D) are illustrated. For simplicity, only a single substrate 12 is illustrated in FIGS. 2A-2D. However, it is to be understood that each of the steps is performed on the panel 10 (FIG. 1) containing multiple substrates 12.

As shown in FIG. 2A, the substrate 12 includes three separate layers 12a, 12b, 12c, that have been pre-formed and then laminated to form a unitary structure. A first substrate layer 12a includes a first side 22 of the substrate 12. A second substrate layer 12b forms a middle portion of the substrate 12. A third substrate layer 12c includes a second side 24 of the substrate. The first side 22 and the second side 24 of the substrate 12 are generally planar opposing surfaces which are substantially parallel to one another.

By way of example, a representative thickness "T" (FIG. 2A) of the substrate 12 can be from 0.5 mm to 3.0 mm. A representative length "L" (FIG. 4) of the substrate 12 can be from 1 mm to 50 mm. A representative width "W" (FIG. 4) of the substrate 12 can be from 1 mm to 50 mm.

A die mounting cavity 18 is formed in the substrate 12 proximate to the second side 24 of the substrate 12. The die mounting cavity 18 is configured to receive a semiconductor die 20 (FIG. 2B). The die mounting cavity 18 can have a peripheral outline that corresponds to a peripheral outline of the die 20. In the illustrative embodiment, the peripheral outline is rectangular, but can also be square or other polygonal shape.

The die mounting cavity 18 can be slightly larger than the die 20 (e.g., a few mils on each side) to permit insertion of the die 20 into the cavity 18. A representative size of the die mounting cavity 18 along a first side S1 (FIG. 2A) can be from 0.3 mm to 12.5 mm. A representative size of the die mounting cavity along a second side "S2" (FIG. 3) can be from 0.3 mm to 12.5 mm. In addition, a depth "D" (FIG. 2A) of the die mounting cavity 18 can be approximately equal to a thickness of the die 20 to preserve a planarity of the second side 24 of the substrate 22 with the die 20 mounted to the cavity 18. A representative depth "D" for the die mounting cavity 18 can be from 0.10 mm to 1.0 mm. Still further, outside edges of the die mounting cavity 18 can be chamfered, or radiused, to facilitate insertion of the die 20 into the cavity 18.

The substrate 12 also includes a wire bonding cavity 26 formed in the substrate 12 proximate to the first side 22 of the substrate 12. The wire bonding cavity 26 is sized to protect bond wires 28 (FIG. 2C) or a similar electrical path. Additionally, the wire bonding cavity 26 is configured to contain an encapsulant 30 that will subsequently be deposited into the wire bonding cavity 26. In the illustrative embodiment, the wire bonding cavity 26 has a peripheral outline and a depth that are about the same as the die mounting cavity 18.

The substrate 12 also includes an interconnect opening 32 formed through the substrate 12 from the die mounting cavity 18 to the wire bonding cavity 26. The interconnect opening 32 is configured to provide access to the die 20 (FIG. 2B) for wire bonding the bond wires 28 to die bond pads 34 (FIG. 2B). As shown in FIG. 3, the interconnect opening 32 has a generally rectangular shaped peripheral configuration. In addition, the interconnect opening 32 is located to align with the die bond pads 34, when the die 20 is mounted within the die mounting cavity 18. A representative width "w" (FIG. 3) of the interconnect opening 32 can be from 0.2 mm to 45 mm. A representative thickness "T1" of the portion of the substrate 12 which forms the interconnect opening 32 can be from 0.1 mm to 0.5 mm.

With the substrate 12 comprising a glass resin, or a plastic material, the die mounting cavity 18, the wire bonding cavity 26 and the interconnect opening 32 can be formed with required sizes and shapes using an injection molding process. With the substrate 12 comprising a ceramic, a lamination process can be used to define the die mounting cavity 18, the wire bonding cavity 26 and the interconnect opening 26. With the substrate 12 comprising silicon, an etch process can be used to etch the die mounting cavity 18, the wire bonding cavity 26 and the interconnect opening 32. One suitable wet etchant for etching silicon is a solution of KOH and H.sub.2 O. This type of etching is also known as bulk micro machining.

The substrate 12 also includes patterns of conductors 36 formed on the first side 22. As shown in FIG. 2A, the conductors 36 extend into the wire bonding cavity 26. In addition, the conductors 36 include bond pads 38 to which the bond wires 28 are wire bonded. Also, the conductors 36 are in electrical communication with contact pads 40 on the first side 22 of the substrate, with interlevel conductors 44 through the substrate 12, and with external contacts 42 on the second side 24 of the substrate 12. FIG. 3 illustrates an exemplary layout for the conductors 36, the bond pads 38 and the contact pads 40.

As shown in FIG. 2D, the contact pads 40 are adapted for bonding to external contacts 42 on an adjacent substrate 12A (FIG. 2D). The adjacent substrate 12A has a configuration that is substantially the same as the configuration of the substrate 12. As will be further explained, a bonding process, such as reflow of a solder material, or curing of a conductive elastomer material, can be used to bond the external contacts 42 on the adjacent substrate 12A to the contact pads 40 on the substrate 12. With the adjacent external contacts 42 comprising a solder material, the contact pads 40 preferably comprise a solder wettable material such as copper. In order to facilitate the bonding process, a pattern of the contact pads 40 on the first side 22 of the substrate 12, exactly matches a pattern of the external contacts on the second side 24 of the substrate 12.

The conductors 36, bond pads 38 and contact pads 40 can be fabricated using a conventional metallization process. For example, a metal layer, such as copper, can be formed on the first side 22 of the substrate 12 using foil lamination, electrolytic plating, electroless plating, or CVD deposition. A resist layer can then be deposited on the metal layer, and patterned using photolithography to form a resist mask. The resist mask can then be used to subtractively etch the metal layer to form the conductors 36, the bond pads 38 and the contact pads 40. Alternately, the conductors 36, bond pads 38 and contact pads 40 can be formed using an additive process in which a resist mask is formed and then used to plate a metal such as copper in the required pattern. A seed or nucleation step can also be employed to prep the surface of the substrate 12 for plating.

As shown in FIG. 2A, the interlevel conductors 44 electrically connect the contact pads 40 on the first side 22 of the substrate 12, to the external contacts 42 on the second side 24 of the substrate 12. The interlevel conductors 44 comprise holes 46 in the substrate 12 which contain an electrically conductive material. Depending on the material of the substrate 12, the holes 46 for the interlevel conductors 44 can be formed using a suitable process such as drilling, punching, molding or etching. Preferably, formation of the holes