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Direct connect interconnect for testing semiconductor dice and wafers    
United States Patent6025730   
Link to this pagehttp://www.wikipatents.com/6025730.html
Inventor(s)Akram; Salman (Boise, ID); Wark; James M. (Boise, ID); Farnworth; Warren M. (Nampa, ID)
AbstractAn interconnect and system for testing semiconductor dice, and a test method using the interconnect are provided. The interconnect includes a substrate having patterns of contact members for electrically contacting the dice. The interconnect also includes patterns of conductors for providing electrical paths to the contact members. In addition, the interconnect includes contact receiving cavities configured to retain electrical connectors of a testing apparatus in electrical communication with the conductors. A die level test system includes the interconnect mounted to a temporary package for a singulated die. In the die level test system, the interconnect provides direct electrical access from testing circuitry to the die. A wafer level test system includes the interconnect mounted to a probe card fixture of a wafer probe handler. In the wafer level test system, the contact receiving cavities can be configured to support and align the interconnect to the probe card fixture.



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Drawing from US Patent 6025730
Direct connect interconnect for testing semiconductor dice and wafers - US Patent 6025730 Drawing
Direct connect interconnect for testing semiconductor dice and wafers
Inventor     Akram; Salman (Boise, ID); Wark; James M. (Boise, ID); Farnworth; Warren M. (Nampa, ID)
Owner/Assignee     Micron Technology, Inc. (Boise, ID)
Patent assignment
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Publication Date     February 15, 2000
Application Number     08/818,456
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     March 17, 1997
US Classification    
Int'l Classification    
Examiner     Ballato; Josie
Assistant Examiner     Solis; Jose M.
Attorney/Law Firm     Gratton; Stephen A.
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Patent Tags     direct connect interconnect testing semiconductor dice wafers
   
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5929647
Akram
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Hembree
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Akram
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 Technical Review Submit all comments and votes
 Claims Submit all comments and votes
 


What is claimed is:

1. In a test system for testing a semiconductor die including testing circuitry for applying test signals to the die and an electrical connector in electrical communication with the testing circuitry, an interconnect for establishing temporary electrical communication between the die and the testing circuitry comprising:

a substrate;

a contact member on the substrate configured to electrically contact a contact location on the die;

a cavity in the substrate configured to retain the electrical connector; and

a conductor on the substrate in electrical communication with the contact member and extending into the cavity, the conductor configured to form a non-bonded electrical connection with the electrical connector retained in the cavity, and provide a direct electrical path from the electrical connector to the contact member.

2. The interconnect of claim 1 wherein the cavity comprises a groove and the electrical connector comprises a tip portion configured for mating engagement with the groove.

3. The interconnect of claim 1 wherein the cavity comprises a groove and the electrical connector comprises a spring member configured to apply a biasing force to the groove.

4. The interconnect of claim 1 wherein the contact location on the die comprises a bump, and the contact member on the interconnect comprises a depression configured to retain the bump.

5. The interconnect of claim 1 wherein the contact location on the die comprises a planar pad, and the contact member on the interconnect comprises a projection configured to penetrate the pad.

6. In a test system for testing a semiconductor die including testing circuitry for applying test signals to the die and an electrical connector in electrical communication with the testing circuitry, an interconnect for establishing temporary electrical communication between the die and the testing circuitry comprising:

a substrate;

a contact member on the substrate configured to electrically engage a contact location on the die;

a cavity in the substrate sized and shaped to retain a tip portion of the electrical connectors and

a conductor on the substrate in electrical communication with the contact member, the conductor comprising a portion within the cavity configured to electrically engage the tip portion of the electrical connector and provide a direct electrical path to the contact member.

7. The interconnect of claim 1 wherein the cavity comprises a groove located proximate to an edge of the substrate.

8. The interconnect of claim 1 wherein the cavity comprises an open ended groove extending from a first edge to a second edge of the interconnect.

9. An interconnect for testing a semiconductor die comprising:

a substrate;

a contact member on the substrate comprising a conductive layer configured to electrically engage a contact location on the die;

a conductor on the substrate in electrical communication with the conductive layer; and

a cavity in the substrate at least partially covered by the conductor and configured to retain an electrical connector of a testing apparatus, the conductor configured to form a non-bonded electrical connection with the electrical connector retained in the cavity to provide a direct electrical path from the electrical connector to the contact member.

10. The interconnect of claim 9 wherein the interconnect comprises a plurality of contact members and conductors, and the cavity comprises a groove configured to retain a plurality of electrical connectors of the testing apparatus in electrical communication with the conductors.

11. The interconnect of claim 9 wherein the connector comprises a spring member and the cavity comprises a groove having a size and a shape corresponding to the connector.

12. The interconnect of claim 9 wherein the cavity comprises an open ended groove extending from a first edge to a second edge of the interconnect.

13. The interconnect of claim 9 wherein the interconnect comprises a temporary package configured to house the die for testing.

14. In a temporary package configured to house a semiconductor die for testing, an interconnect on the temporary package configured to form temporary electrical connections between the die and testing circuitry, the interconnect comprising:

a substrate;

a plurality of contact members on the substrate configured to electrically engage a plurality of contact locations on the die;

a plurality of conductors on the substrate in electrical communication with the contact members; and

a cavity in the substrate configured to retain a plurality of electrical connectors in electrical communication with the testing circuitry;

the conductors comprising portions within the cavity configured to form non-bonded electrical connections with the electrical connectors retained in the cavities, to provide direct electrical paths from the electrical connectors to the conductors and the contact members.

15. The interconnect of claim 14 wherein the temporary package is configured for mounting to a test socket, and the electrical connectors are contained on the test socket.

16. The interconnect of claim 14 wherein the temporary package comprises a base and a force applying mechanism for biasing the die, and the interconnect is mounted to the base such that the force applying mechanism biases the die against the interconnect.

17. The interconnect of claim 14 wherein the contact locations on the die comprise bumps, and the contact members on the interconnect comprise depressions configured to retain the bumps.

18. The interconnect of claim 14 wherein the contact locations on the die comprise planar pads, and the contact members on the interconnect comprise projections configured to penetrate the pads.

19. The interconnect of claim 14 wherein the interconnect comprises a pair of cavities located along opposite edges thereof.

20. In a temporary package configured to house a semiconductor die for testing, an interconnect on the temporary package configured to form temporary electrical connections between the die and testing circuitry, the interconnect comprising:

a substrate;

a contact member on the substrate at least partially covered with a conductive layer configured to electrically engage a contact location on the die;

a cavity in the substrate sized and shaped to retain an electrical connector in electrical communication with the testing circuitry; and

a conductor on the substrate in electrical communication with the conductive layer and extending into the cavity, the conductor configured to form a non-bonded electrical connection with the electrical connector retained in the cavity to provide a direct electrical path from the electrical connector to the contact member.

21. The interconnect of claim 20 wherein the temporary package comprises a base for mounting the interconnect and a force applying mechanism for biasing the die against the interconnect.

22. The interconnect of claim 20 wherein the electrical connector comprises a spring member configured to exert a biasing force on the cavity.
 Description Submit all comments and votes
 


FIELD OF THE INVENTION

This invention relates generally to semiconductor manufacture and more particularly to an improved interconnect for testing semiconductor dice and wafers. The invention also relates to a test method and system that employ the interconnect.

BACKGROUND OF THE INVENTION

For testing semiconductor dice, temporary electrical connections must be made to the integrated circuits on the dice. Typically, the electrical connections are made through contact locations, such as bond pads or test pads, formed on the faces of the dice. Testing at the wafer level can be performed using probe cards and a wafer probe handler. Probe cards include probe needles that electrically contact the contact locations on the wafer. Test circuitry associated with the wafer probe handler applies test signals through the probe card to the integrated circuits.

Testing can also be performed on dice that have been singulated from the wafer. In this case, temporary packages are adapted to house a single bare die on a burn-in board or other test apparatus. The temporary packages typically include an interconnect having contact members configured to electrically contact the contact locations on the die.

With wafer level testing, electrical connections must be made to the probe card. With die level testing, electrical connections must be made to the interconnect for the temporary package. These electrical connections are typically bonded connections. With bonded connections it can be difficult to separate a probe card from the wafer handler, or an interconnect from a temporary package, without damage. This makes replacing and interchanging the probe cards and interconnects difficult.

Another requirement of the connections to a probe card or interconnect is that the electrical connections must sometimes be capable of transmitting signals at high test speeds (e.g., 500 MHz). It is desirable to transmit test signals without generating parasitic inductance and cross coupling (i.e., "cross talk").

Often times the electrical connections with the probe card or interconnect are sources of parasitic inductance. For example, with temporary packages having wire bonded interconnects, it can be difficult to accurately space the bond wires from one another. Accordingly, capacitive coupling can occur between adjacent bond wires generating noise and spurious signals.

The problems of parasitic inductance and cross coupling can be compounded by the large number of bond pads contained on later generations of semiconductor dice. In particular, a large number of bond pads requires a corresponding number of electrical connections to the probe card or interconnect. It can be difficult to make these electrical connections without forming parasitic inductors and initiating cross talk and interconductor noise.

The present invention is directed to an improved interconnect capable of high speed testing of either wafers or singulated dice, with reduced parasitics inductance. In addition, non-bonded electrical connections can be made to the interconnect, such that removing and replacing the interconnect is facilitated.

SUMMARY OF THE INVENTION

In accordance with the present invention, an improved interconnect and system for testing semiconductor dice, and a test method using the interconnect are provided. The interconnect includes a substrate having contact members configured to make temporary electrical connections with contact locations on the dice. The contact members can be configured to electrically contact bumped contact locations on the dice, such as solder bumps, or flat contact locations on the dice, such as metal bond pads.

The interconnect also includes patterns of conductors in electrical communication with the contact members. In addition, contact receiving cavities are formed on the substrate to facilitate an electrical connection from a testing apparatus to the conductors. Each separate conductor is configured to connect to a mating electrical connector of the testing apparatus, such as a spring clip, socket contact, spring loaded pin, or other member. The contact receiving cavities permit non-bonded, direct electrical connections to be made from testing circuitry to the interconnect.

The interconnect substrate can be formed of silicon, or an electrically insulating material, such as ceramic. For dice with bumped contact locations, the contact members can comprise depressions formed in the substrate and covered with a conductive layer. The depressions can be formed at the same time as the contact receiving cavities using a bulk micro-machining process. Alternately, for dice with flat contact locations, the contact members can include penetrating projections covered with a conductive layer.

The interconnect can be configured for use with a die level test system or a wafer level test system. With a die level test system, the interconnect can be mounted within a temporary package for a single die. The temporary package is adapted for use with a testing apparatus, such as a burn-in board, in electrical communication with testing circuitry. The temporary package can include a base and a force applying mechanism for biasing the die and interconnect together. In the die level test system, the interconnect establishes temporary electrical communication with the contact locations on the die, and provides conductive paths to and from the testing circuitry to the contact locations.

With a wafer level test system, the interconnect can be configured to contact semiconductor dice contained on a wafer. A conventional testing apparatus, such as a wafer probe handler, can be used to support the interconnect and the wafer. For mounting the interconnect to the testing apparatus, a conventional probe card fixture can be modified for use with the interconnect. The probe card fixture can include an opening for receiving the interconnect. In addition, electrical connectors can be formed on the probe card fixture, along a periphery of the opening, for physically supporting, aligning and electrically connecting the interconnect. In this embodiment, the electrical connectors on the probe card fixture engage the contact receiving cavities on the interconnect. In addition, a biasing member can be used to cushion forces applied by the testing apparatus to the interconnect, and to allow the contact members to self planarize to the contact locations on the wafer. The biasing member can be formed of a compressible elastomer or as a metal filled elastomer configured to dissipate he