Direct connect interconnect for testing semiconductor dice and wafers

Claims

What is claimed is:

1. In a test system for testing a semiconductor die including testing circuitry for applying test signals to the die and an electrical connector in electrical communication with the testing circuitry, an interconnect for establishing temporary electrical communication between the die and the testing circuitry comprising:

a substrate;

a contact member on the substrate configured to electrically contact a contact location on the die;

a cavity in the substrate configured to retain the electrical connector; and

a conductor on the substrate in electrical communication with the contact member and extending into the cavity, the conductor configured to form a non-bonded electrical connection with the electrical connector retained in the cavity, and provide a direct electrical path from the electrical connector to the contact member.

2. The interconnect of claim 1 wherein the cavity comprises a groove and the electrical connector comprises a tip portion configured for mating engagement with the groove.

3. The interconnect of claim 1 wherein the cavity comprises a groove and the electrical connector comprises a spring member configured to apply a biasing force to the groove.

4. The interconnect of claim 1 wherein the contact location on the die comprises a bump, and the contact member on the interconnect comprises a depression configured to retain the bump.

5. The interconnect of claim 1 wherein the contact location on the die comprises a planar pad, and the contact member on the interconnect comprises a projection configured to penetrate the pad.

6. In a test system for testing a semiconductor die including testing circuitry for applying test signals to the die and an electrical connector in electrical communication with the testing circuitry, an interconnect for establishing temporary electrical communication between the die and the testing circuitry comprising:

a substrate;

a contact member on the substrate configured to electrically engage a contact location on the die;

a cavity in the substrate sized and shaped to retain a tip portion of the electrical connectors and

a conductor on the substrate in electrical communication with the contact member, the conductor comprising a portion within the cavity configured to electrically engage the tip portion of the electrical connector and provide a direct electrical path to the contact member.

7. The interconnect of claim 1 wherein the cavity comprises a groove located proximate to an edge of the substrate.

8. The interconnect of claim 1 wherein the cavity comprises an open ended groove extending from a first edge to a second edge of the interconnect.

9. An interconnect for testing a semiconductor die comprising:

a substrate;

a contact member on the substrate comprising a conductive layer configured to electrically engage a contact location on the die;

a conductor on the substrate in electrical communication with the conductive layer; and

a cavity in the substrate at least partially covered by the conductor and configured to retain an electrical connector of a testing apparatus, the conductor configured to form a non-bonded electrical connection with the electrical connector retained in the cavity to provide a direct electrical path from the electrical connector to the contact member.

10. The interconnect of claim 9 wherein the interconnect comprises a plurality of contact members and conductors, and the cavity comprises a groove configured to retain a plurality of electrical connectors of the testing apparatus in electrical communication with the conductors.

11. The interconnect of claim 9 wherein the connector comprises a spring member and the cavity comprises a groove having a size and a shape corresponding to the connector.

12. The interconnect of claim 9 wherein the cavity comprises an open ended groove extending from a first edge to a second edge of the interconnect.

13. The interconnect of claim 9 wherein the interconnect comprises a temporary package configured to house the die for testing.

14. In a temporary package configured to house a semiconductor die for testing, an interconnect on the temporary package configured to form temporary electrical connections between the die and testing circuitry, the interconnect comprising:

a substrate;

a plurality of contact members on the substrate configured to electrically engage a plurality of contact locations on the die;

a plurality of conductors on the substrate in electrical communication with the contact members; and

a cavity in the substrate configured to retain a plurality of electrical connectors in electrical communication with the testing circuitry;

the conductors comprising portions within the cavity configured to form non-bonded electrical connections with the electrical connectors retained in the cavities, to provide direct electrical paths from the electrical connectors to the conductors and the contact members.

15. The interconnect of claim 14 wherein the temporary package is configured for mounting to a test socket, and the electrical connectors are contained on the test socket.

16. The interconnect of claim 14 wherein the temporary package comprises a base and a force applying mechanism for biasing the die, and the interconnect is mounted to the base such that the force applying mechanism biases the die against the interconnect.

17. The interconnect of claim 14 wherein the contact locations on the die comprise bumps, and the contact members on the interconnect comprise depressions configured to retain the bumps.

18. The interconnect of claim 14 wherein the contact locations on the die comprise planar pads, and the contact members on the interconnect comprise projections configured to penetrate the pads.

19. The interconnect of claim 14 wherein the interconnect comprises a pair of cavities located along opposite edges thereof.

20. In a temporary package configured to house a semiconductor die for testing, an interconnect on the temporary package configured to form temporary electrical connections between the die and testing circuitry, the interconnect comprising:

a substrate;

a contact member on the substrate at least partially covered with a conductive layer configured to electrically engage a contact location on the die;

a cavity in the substrate sized and shaped to retain an electrical connector in electrical communication with the testing circuitry; and

a conductor on the substrate in electrical communication with the conductive layer and extending into the cavity, the conductor configured to form a non-bonded electrical connection with the electrical connector retained in the cavity to provide a direct electrical path from the electrical connector to the contact member.

21. The interconnect of claim 20 wherein the temporary package comprises a base for mounting the interconnect and a force applying mechanism for biasing the die against the interconnect.

22. The interconnect of claim 20 wherein the electrical connector comprises a spring member configured to exert a biasing force on the cavity.