An analog compensation circuit for providing process/voltage/temperature (PVT) bias compensation signals for input/output (I/O) circuitry within an integrated circuit includes a first current source coupled to a first node. A first load coupled to the first current source and a second node provides a first reference voltage. A voltage divider coupled between the first and second nodes provides a current source bias voltage to the first current source. A differential amplifier generates a first bias compensation signal as feedback for the first current source in accordance with the difference between the first reference voltage and a second reference voltage. With the addition of logic level bias converters, the compensation circuitry is capable of providing bias compensation signals to multiple logic families. The bias compensation signals can be applied to current sources used to control the functioning of integrated circuit I/O circuitry so that the I/O circuitry operates substantially independently of PVT variations.
A low voltage different signaling (LVDS) includes an LVDS transmitter and an LVDS receiver. The LVDS transmitter includes a feedback compensation circuit, which adjusts and stabilizes the analog image signal to be transmitted to the LVDS receiver according to the voltage difference of the analog image signal and a base signal. The feedback compensation circuit includes a voltage-to-current converting circuit and a pair of current mirror circuits.
A low voltage current mirror circuit (also referred to as a bias circuit) for establishing a plurality of bias voltages from an input current supplied to an input terminal of the circuit includes an input stage, a current stage connected to the input stage, a feedback stage connected to the current stage, a reference bias stage connected to the feedback stage and the current stage. The circuit establishes first and second bias voltages suitable for biasing current sources of a first type, and third and fourth bias voltages suitable for biasing current sources of a second type complementary to the first type. The bias voltages track the input current over variations in at least one of process, temperature and power supply voltage.
A low voltage current mirror circuit (also referred to as a bias circuit) for establishing a plurality of bias voltages from an input current supplied to an input terminal of the circuit includes an input stage, a current stage connected to the input stage, a feedback stage connected to the current stage, a reference bias stage connected to the feedback stage and the current stage. The circuit establishes first and second bias voltages suitable for biasing current sources of a first type, and third and fourth bias voltages suitable for biasing current sources of a second type complementary to the first type. The bias voltages track the input current over variations in at least one of process, temperature and power supply voltage.
A low voltage current mirror circuit (also referred to as a bias circuit) for establishing a plurality of bias voltages from an input current supplied to an input terminal of the circuit includes an input stage, a current stage connected to the input stage, a feedback stage connected to the current stage, a reference bias stage connected to the feedback stage and the current stage. The circuit establishes first and second bias voltages suitable for biasing current sources of a first type, and third and fourth bias voltages suitable for biasing current sources of a second type complementary to the first type. The bias voltages track the input current over variations in at least one of process, temperature and power supply voltage.
An analog process/voltage/temperature (PVT) compensated buffer includes a differential amplifier providing a first output signal indicative of a difference between an input signal and a reference signal. The input signal is compatible with a first type of logic. An active gain stage is coupled to translate the first output signal to a second output signal. The second output signal is compatible with a second type of logic. The differential amplifier and the active gain stage are coupled to receive a process/voltage/temperature (PVT) compensation signal. In one embodiment, the first type of logic is Gunning Transceiver Logic (GTL) and the second type of logic is complementary metal oxide semiconductor (CMOS) logic.
