A processing system 100 is disclosed which includes a system master 101, a system bus 102 coupled to the master, and a plurality of bus interface circuits 106 coupled to bus 102. A first one of the bus interfaces 106 includes a mapping signal input coupled to the master and a mapping signal output, the first bus interface 106 operable to latch-in at least one first selected address bit presented by the master on the system bus in response to a mapping enable signal received at the mapping signal input from the master 101. A second bus interface 106 is provided coupled to the bus 102 and having a mapping signal input coupled to the mapping signal output of first bus interface 106, the second bus interface 106 operable to latch-in at least one second selected address bit presented by the master 101 on the bus 102 in response to a second mapping enable signal received at the mapping input of the second bus interface 106 from the first bus interface 106.
A method is provided for rendering display blocks on a video display device of a computer processing system having an existing display driver. The method includes the step of assigning each of a plurality of n video adapters to an m.sup.th display subregion of the display device. A call to a draw function of the existing display driver is received. The draw function corresponds to a particular shape to be drawn and includes starting and ending coordinates. The m.sup.th display subregion that drawing of the shape is to begin on is calculated from the starting coordinates. A function of the existing display driver is called by calling an address stored in the filter driver of a routine corresponding to the called function. The called function corresponds to the received draw function. A segment of the shape is rendered on the calculated m.sup.th display subregion by the n.sup.th display adapter corresponding thereto. A traversal is made to the n.sup.th video adapter corresponding to a next segment of the shape. The next segment of the shape is rendered on the m.sup.th display subregion corresponding to the traversed n.sup.th video adapter. The traversal and second rendering step are repeated until all segments of the shape have been rendered.
An apparatus comprising one or more drive portions and a controller. The one or more drive portions may each comprise one or more drives. The controller may be configured to map correctly correlating addresses to the one or more drives.
A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address.
A programmable logic IC and a ROM are set in a controller section between a display and ICs (an IC for wireless communication and an IF IC). In each of plural program sets stored in the ROM, a series of operation up to the time that image data, after being read from the IC for wireless communication and converted into a logic signal, is sent to the display is described. On the other hand, the programmable logic IC changes the program set being read, according to what is displayed on the display, television images, a monitor image supplied from a computer, or image data from a memory card. This makes it possible to attain an image-display-device controller circuit that has a small circuit scale, consumes a small amount of power, and is small in size and weight are small, but can change operation.
A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address.
