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Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same    
United States Patent6026050   
Link to this pagehttp://www.wikipatents.com/6026050.html
Inventor(s)Baker; Russel Jacob (Meridian, ID); Manning; Troy A. (Meridian, ID)
AbstractA system for adjusting the phase of an internal clock signal relative to an external clock signal in a packetized dynamic random access memory device. The system applies a plurality of initialization packets of the memory device that are captured in a shift register responsive to a transition of the internal clock signal. However, the phase of the internal clock signal is sequentially incremented after each initialization packet has been captured in the shift register. After a plurality of initialization packets have been captured, an evaluation circuit identifies which phases of the internal clock signal clocked the shift register at the proper time to accurately capture each initialization packet. A single phase of the internal clock signal is then selected from within the range of internal clock signal phases that successfully captured initialization packets. This selected phase of the internal clock signal is used during normal operation of the memory device.



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Drawing from US Patent 6026050
Method and apparatus for adaptively adjusting the timing of a clock

     signal used to latch digital signals, and memory device using same - US Patent 6026050 Drawing
Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
Inventor     Baker; Russel Jacob (Meridian, ID); Manning; Troy A. (Meridian, ID)
Owner/Assignee     Micron Technology, Inc. (Boise, ID)
Patent assignment
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Publication Date     February 15, 2000
Application Number     09/248,194
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     February 10, 1999
US Classification    
Int'l Classification    
Examiner     Le; Vu A.
Assistant Examiner    
Attorney/Law Firm     Dorsey & Whitney LLP
Address
Parent Case     CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation of pending U.S. patent application Ser. No. 08/890,055, filed Jul. 9, 1997.
Priority Data    
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Patent Tags     adaptively adjusting timing clock signal used latch digital signals, memory
   
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