An efficient method for identifying potential noise failures in an integrated circuit design by predicting peak noise within a victim circuit of an integrated circuit. Initially, a victim circuit within an integrated circuit is located. An aggressor circuit within the integrated circuit is located which has a physical relationship with the victim circuit, normally proximity. The slope of a signal within the aggressor circuit is analyzed and the coupling currents induced in the victim circuit by the aggressor circuit are computed. The input slope of the aggressor circuit and the physical relationship between the victim circuit and the aggressor circuit are utilized to determine a peak current induced into the victim circuit utilizing modelled coupling capacitance. The peak current and the equivalent impedance of the victim circuit can be utilized to determine peak noise. Noise failures on integrated circuits can be avoided by detecting peak noise which is above acceptable levels.
One embodiment of the present invention provides a system for calibrating a model of a digital circuit to account for noise effects between signal lines. The system operates by first fabricating a digital circuit for calibration purposes. Next, an input signal is applied to an aggressor net within the digital circuit. The system then measures how noise from the input signal affects the amplitude of a signal on a victim net within the digital circuit. Finally, the system adjusts parameters of the circuit model using the measured results.
The present invention includes a system for and a method of determining noise characteristics of a circuit of an integrated circuit. The circuit is classified based on its topology and measured circuit parameters. Noise characteristics are retrieved using the circuit classification and circuit parameters to calculate a noise response. Classification and characterization may be performed on each individual input.
Method and apparatus for detecting and analyzing effects of noise in a digital circuit that arises from a coupling of signals produced by switching of a first gate and a second gate in a timed relationship. Where each of a first gate and a second gate can switch within a selected switching time interval, the gate switching effects are combined and the second gate output signal is analyzed with reference to the first gate input signal. Otherwise, the gate switching effects are not combined. When the second gate output signal satisfies at least one of three criteria, this condition is interpreted as indicating that the second gate permits propagation of a noise pulse produced at the first gate.
Methods of testing for shorts (e.g., bridging defects) between interconnect lines in an integrated circuit. For example, in a design implemented in a programmable logic device (PLD), some interconnect lines are used and others are unused. To test for shorts between the used and unused interconnect lines, both used and unused interconnect lines are driven to a first logic level, and the leakage current is measured. The used interconnect lines are driven to a second logic level, while the unused lines remain at the first logic level. The current is again measured, and the difference between the two measurements is determined. If the difference exceeds a predetermined threshold, the device design combination is rejected. Some embodiments provide methods of testing for shorts between used and unused interconnect lines for a design targeted to a partially defective PLD.
A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
