Source-clock-synchronized memory system and memory unit

Claims

We claim:

1. A source-clock-synchronized memory system for use in apparatus which includes a base board and a memory controller provided on said base board, said source-clock-synchronized memory system comprising:

a memory unit for mounting on said base board,

wherein said memory unit comprises:

a first memory riser board mounted on said base board through a first connector with a plurality of first memory modules mounted on the front surface of said first memory riser board,

a second memory riser board mounted on said base board through a second connector with a plurality of second memory modules mounted on the front surface of said second memory riser board,

wherein said first and second memory riser boards are arranged such that the back surface of said first memory riser board faces the back surface of said second memory riser board, and

a board linking connector for connecting signal lines on said first memory riser board to corresponding signal lines on said second memory riser board,

wherein said signal lines includes address/command and data lines, each being accompanied by clock signal lines, that start from said memory controller, pass through said first connector, are wired to said first memory modules mounted on said first memory riser board sequentially one module after another, pass through said board linking connector and are wired to said second memory modules mounted on said second memory riser board sequentially one module after another, and

wherein at least said data line further passes through said second connector and is connected back to said memory controller in a ring state.

2. A source-clock-synchronized memory system according to claim 1, wherein said address/command line is ended by a matching terminator on said second memory riser board and said clock line further passes through said second connector and is connected back to said memory controller.

3. A source-clock-synchronized memory system according to claim 1, wherein said clock and address/command lines are each ended by a matching terminator on said second memory riser board.

4. A source-clock-synchronized memory system according to claim 1, further comprising:

a switch provided on said base board for connecting said data line wired to said memory controller to either said data line on said first memory riser board passing through said first connector or said data line on said second memory riser board passing through said second connector in accordance with a control signal generated by said memory controller so that data to be written into a desired memory module in said memory unit can be transferred from said memory controller to said desired memory module through said data line by way of said switch and said first connector whereas data read out from a desired memory module in said memory unit can be transferred from said desired memory module to said memory controller through said data line by way of said second connector and said switch.

5. A source-clock-synchronized memory system according to claim 2, further comprising:

a switch provided on said base board for connecting said data line wired to said memory controller to either said data line on said first memory riser board passing through said first connector or said data line on said second memory riser board passing through said second connector in accordance with a control signal generated by said memory controller so that data to be written into a desired memory module in said memory unit can be transferred from said memory controller to said desired memory module through said data line by way of said switch and said first connector whereas data read out from a desired memory module in said memory unit can be transferred from said desired memory module to said memory controller through said data line by way of said second connector and said switch.

6. A source-clock-synchronized memory system according to claim 3, further comprising:

a switch provided on said base board for connecting said data line wired to said memory controller to either said data line on said first memory riser board passing through said first connector or said data line on said second memory riser board passing through said second connector in accordance with a control signal generated by said memory controller so that data to be written into a desired memory module in said memory unit can be transferred from said memory controller to said desired memory module through said data line by way of said switch and said first connector whereas data read out from a desired memory module in said memory unit can be transferred from said desired memory module to said memory controller through said data line by way of said second connector and said switch.

7. A source-clock-synchronized memory system for use in apparatus which includes a base board and a memory controller provided on said base board, said source-clock-synchronized memory comprising:

a memory unit for mounting on said base board,

wherein said memory unit comprises:

a memory riser board mounted on said base board through at least a connector, said memory riser board being provided with a plurality of front memory modules mounted on the front surface of said memory riser board and a plurality of back memory modules mounted on the back surface of said memory riser board,

wherein signal lines including address/command and data lines, each being accompanied by a clock signal line, start from said memory controller, pass through said connector, are wired to said front memory modules mounted on said front surface of said first memory riser board sequentially one module after another, pass through the top of said memory riser board and are wired to said back memory modules mounted on said back surface of said memory riser board sequentially one module after another; and

wherein at least said data line further passes through said connector and is connected back to said memory controller in a ring state.

8. A source-clock-synchronized memory system according to claim 7, wherein said address/command line is ended by a matching terminator on said back surface of said memory riser board and said clock line further passes through said connector and is connected back to said memory controller.

9. A source-clock-synchronized memory system according to claim 7, wherein said clock and address/command lines are each ended by a matching terminator on said back surface of said memory riser board.

10. A source-clock-synchronized memory system according to claim 7, further comprising:

a switch provided on said base board for connecting said data line wired to said memory controller to either said data line on said front surface of said memory riser board passing through said connector or said data line on said back surface of said memory riser board passing through said connector in accordance with a control signal generated by said memory controller so that data to be written into a desired memory module in said memory unit can be transferred from said memory controller to said desired memory module through said data line by way of said switch and said connector whereas data read out from a desired memory module in said memory unit can be transferred from said desired memory module to said memory controller through said data line by way of said connector and said switch.

11. A source-clock-synchronized memory system according to claim 8, further comprising:

a switch provided on said base board for connecting said data line wired to said memory controller to either said data line on said front surface of said memory riser board passing through said connector or said data line on said back surface of said memory riser board passing through said connector in accordance with a control signal generated by said memory controller so that data to be written into a desired memory module in said memory unit can be transferred from said memory controller to said desired memory module through said data line by way of said switch and said connector whereas data read out from a desired memory module in said memory unit can be transferred from said desired memory module to said memory controller through said data line by way of said connector and said switch.

12. A source-clock-synchronized memory system according to claim 9, further comprising:

a switch provided on said base board for connecting said data line wired to said memory controller to either said data line on said front surface of said memory riser board passing through said connector or said data line on said back surface of said memory riser board passing through said connector in accordance with a control signal generated by said memory controller so that data to be written into a desired memory module in said memory unit can be transferred from said memory controller to said desired memory module through said data line by way of said switch and said connector whereas data read out from a desired memory module in said memory unit can be transferred from said desired memory module to said memory controller through said data line by way of said connector and said switch.

13. A source-clock-synchronized memory system for use in apparatus which includes a base board, and a memory controller provided on said base board, said source-clock-synchronized memory system comprising:

a memory unit provided on said base board,

wherein said memory unit comprises:

a memory riser board mounted on said base board through at least a connector with a plurality of memory modules mounted on the front and back surfaces of said memory riser board, and

a switch for connecting a data line wired to said connector to one of two data lines wired to said modules in accordance with a control signal output by said memory controller;

wherein signal lines including address/command lines, each being accompanied by a clock signal line, start from said memory controller, pass through said connector and are wired to said memory modules mounted on the front and back surfaces of said memory riser board sequentially one module after another; and

wherein a data line including said data line wired to said connector and said two data lines wired to said memory modules starts from said memory controller, passes through said connector and said switch, is wired to said memory modules mounted on the front and back surfaces of said memory riser board sequentially one module after another, passes through said switch again and is folded back to said memory controller, said data lines passing to each of said modules from said memory controller in a ring state.

14. A source-clock synchronized memory system according to claim 13, wherein said switch is provided on said memory riser board.

15. A memory unit for use in apparatus which includes a base board and a memory controller provided on said base board, said memory unit comprising:

a first memory riser board mounted on said base board through a first connector with a plurality of first memory modules mounted on the front surface of said first memory riser board;

a second memory riser board mounted on said base board through a second connector with a plurality of second memory modules mounted on the front surface of said second memory riser board,

wherein said first and second memory riser boards are arranged such that the back surface of said first memory riser board faces the back surface of said second memory riser board; and

a board linking connector for connecting signal lines on said first memory riser board to corresponding signal lines on said second memory riser board,

wherein said signal lines address/command and data lines, each being accompanied by a clock signal line, start from contact points on said first connector, are wired to said first memory modules mounted on said first memory riser board sequentially one module after another, pass through said board linking connector and are wired to said second memory modules mounted on said second memory riser board sequentially one module after another, said data lines passing to each of said modules from said memory controller in a ring state, and

wherein at least said data line is further extended to another contact point on said second connector.

16. A memory unit according to claim 15, wherein said contact points on said connector of said memory unit are wired to said memory controller,

wherein ends of signal lines on another memory unit are wired through a connector thereof to said contact points on said connector of said memory unit to form a daisy chain connecting said memory modules of said memory units to said memory controller, and

wherein at least said data line in a last memory unit is further extended from a contact point on a connector of said last memory unit to said memory controller.

17. A memory unit according to claim 15, further comprising:

a first switch, provided on said base board, for connecting first controller-side signal lines wired to said memory controller to first module-side signal lines wired to said memory unit selected from a plurality of memory units by a first control signal generated by said memory controller; and

a second switch, provided on said base board, for connecting second controller-side signal lines wired to said memory controller to second module-side signal lines wired to another memory unit from said plurality of memory units by a second control signal generated by said memory controller,

wherein data is written into one of said memory modules in said memory unit whose first module-side signal lines are connected by said first switch, and

wherein data is read out from one of said memory module in said another memory unit whose second module-side signal lines are connected by said second switch.

18. A memory unit for use in apparatus which includes a base board and a memory controller provided on said base board, said memory unit comprising:

a memory riser board mounted on said base board through at least a connector with a plurality of front memory modules mounted on the front surface of said memory riser board and a plurality of back memory modules mounted on the back surface of said memory riser board; and

a plurality of signal lines including address/command and data lines, each being accompanied by a clock signal line, said signal lines start from contact points on said connector, are wired to said front memory modules mounted on said front surface of said first memory riser board sequentially one module after another, pass through the top of said memory riser board and are wired to said back memory modules mounted on said back surface of said memory riser board sequentially one module after another, said data lines passing to each of said modules from said memory controller in a ring state,

wherein at least said data line is further extended to another contact point on said connector.

19. A memory unit according to claim 18, wherein said contact points on said connector of said memory unit are wired to said memory controller,

wherein ends of signal lines on another memory unit are wired through a connector thereof to said contact points on said connector of said memory unit to form a daisy chain connecting said memory modules of said memory units to said memory controller; and

wherein at least said data line in a last memory unit is further extended from a contact point on a connector of said last memory unit to said memory controller.

20. A memory unit according to claim 18, further comprising:

a first switch provided on said base board, for connecting first controller-side signal lines wired to said memory controller to first module-side signal lines wired to said memory unit selected from a plurality of memory units by a first control signal generated by said memory controller; and

a second switch provided on said base board for connecting second controller-side signal lines wired to said memory controller to second module-side signal lines wired to another memory unit from said plurality of memory units by a second control signal generated by said memory controller,

wherein data is written into one of said memory modules in said memory unit whose first module-side signal lines are connected by said first switch, and

wherein data is read out from one of said memory modules in said another memory unit whose second module-side signal lines are connected by said second switch.

21. A memory unit according to claim 20, wherein said first and second controller-side signal lines are disconnected from said memory controller; and

wherein a third switch is further provided for connecting controller-side signal lines wired to said memory controller to said first controller-side signal lines wired to said first switch or said controller-side signal lines wired to said second switch based on a third control signal generated by said memory controller.

22. A memory unit according to claim 20, wherein said first and second switches can each be controlled to set said first or second controller-side signal lines wired to said memory controller to a high-impedance state.

23. A connector for removably mounting a memory unit which includes a memory riser board having a plurality of memory modules mounted on the front surface thereof, on a base board apparatus so as to connect signal lines on said memory unit to signal-line wires on said base board, said connector comprising:

a connector box having an accepting mouth for accepting and firmly holding said memory riser board of said memory unit, wherein a shape of said accepting mouth corresponds to a cross section of said memory riser board;

a first pin connected to one of said signal-line wires on said base board and extended from said base board to said accepting mouth; and

a second pin connected to another of said separated signal-line wires on said base board and extended from said base board to said accepting mouth,

wherein, when said memory riser board is not mounted, said first pin comes in contact with said second pin, electrically connecting signal-line wires connected to said pins to each other and when said memory riser board is mounted said first pin comes in contact with a signal line on the front surface of said memory riser board, electrically connecting said first pin to said signal line on said front surface whereas said second pin comes in contact with a signal line on the back surface of said memory riser board, electrically connecting said second pin to said signal line on said back surface.

24. A connector according to claim 23, wherein said first and second pins are each made of an elastic material, and

wherein when said memory riser board is not mounted, said first pin comes in contact with said second pin due to an elastic property of said material.

25. A connector for connecting first and second memory riser boards of a memory unit which is included in apparatus having a base board upon which is mounted said memory unit and a memory controller, wherein said first and second memory riser boards each has mounted on a front surface thereof a plurality of memory modules each being connected sequentially one module after another to signal lines including address/command and data lines, each being accompanied by a clock signal line, wherein said signal lines start from said memory controller, and are sequentially connected to memory modules on said first memory riser board and then said second memory riser board, wherein at least said data line from said second memory riser board is connected back to said memory controller in a ring state, said connector comprising:

a plurality of connectors for connecting signal lines on said first memory riser board to corresponding signal lines on said second memory riser board.

26. An information processing system comprising:

a base board;

a memory controller provided on said base board; and

a memory unit mounted on said base board for storing information under control of said memory controller,

wherein said memory unit comprises:

a first memory riser board mounted on said base board through a first connector with a plurality of first memory modules mounted on the front surface of said first memory riser board,

a second memory riser board mounted on said base board through a second connector with a plurality of second memory modules mounted on the front surface of said second memory riser board,

wherein said first and second memory riser boards are arranged such that the back surface of said first memory riser board faces the back surface of said second memory riser board, and

a board linking connector for connecting signal lines on said first memory riser board to corresponding signal lines on said second memory riser board,

wherein said signal lines include address/command and data lines, each being accompanied by a clock signal line, that start from said memory controller, path through said first connector, are wires to said first memory modules mounted on said first memory riser board sequentially one module after another, pass through said board making connector and are wired to said second memory modules mounted on said second memory riser board sequentially one module after another, and

wherein at least said data line further passes through said second connector and is mounted back to said memory controller in a ring state.

27. An information processing system according to claim 26, wherein said information processing system is a server.

28. An information processing system, comprising:

a base board;

a memory controller provided on said base board; and

a memory unit mounted on said base board for storing data under control of said memory controller,

wherein said memory unit comprises:

a memory riser board mounted on said base board through at least a connector, said memory riser board being provided with a plurality of front memory modules mounted on the front surface of said memory riser board and a plurality of back memory modules mounted on the back surface of said memory riser board,

wherein signal lines including address/command and data lines, each being accompanied by a clock signal line, start from said memory controller, pass through said connector, are wired to said front memory modules mounted on said front surface of said first memory riser board sequentially one module after another, pass through the top of said memory riser board and are wired to said back memory modules mounted on said back surface of said memory riser board sequentially one module after another; and

wherein at least said data line further passes through said connector and is connected back to said memory controller in a ring state.

29. An information processing system according to claim 28, wherein said information processing system is a server.

30. An information processing system, comprising:

a base board;

a memory controller provided on said base board; and

a memory unit mounted on said base board for storing data under control of said memory controller,

wherein said memory unit comprises:

a memory riser board mounted on said base board through at least a connector with a plurality of memory modules mounted on the front and back surfaces of said memory riser board, and

a switch for connecting a data line wired to said connector to one of two data lines wired to said modules in accordance with a control signal output by said memory controller;

wherein signal lines including address/command lines, each being accompanied by a clock signal line, start from said memory controller, pass through said connector and are wired to said memory modules mounted on the front and back surfaces of said memory riser board sequentially one module after another; and

wherein a data line including said data line wired to said connector and said two data lines wired to said memory modules starts from said memory controller, passes through said connector and said switch, is wired to said memory modules mounted on the front and back surfaces of said memory riser board sequentially one module after another, passes through said switch again and is folded back to said memory controller, said data lines passing to each of said modules from said memory controller in a ring state.

31. An information processing system according to claim 30, wherein said information processing system is a server.

BACKGROUND OF THE INVENTION

The present invention relates to a technology for exchanging signals between a memory controller and a memory device employed in an information processing apparatus. More particularly, the present invention relates to a memory system for transmitting signals at a high speed to a plurality of memory devices connected to a common transmission line.

In order to implement the IEEE P1596.4 (SyncLink), there has been proposed RamLink, a high-speed memory system employed in an information processing apparatus as disclosed in "SyncLink: A Proposal for an Implementation of IEEE P1596.4 `Ramlink` Optimized for Small (Single-Board) Memory System" by H. Wiggers, Hewlett Packard Company, which was published Mar. 23, 1995, pp 1-6. RamLink is a DRAM system for implementing a transfer speed equal to or higher than 500 Mbytes/s as a bandwidth. Five different topologies have been proposed. As a characteristic of a fourth option among the five proposed topologies, there is provided a system wherein read data is folded in order to reduce the number of skews.

According to this technique, a memory system comprises memory modules 10-0 to 10-7 each incorporating 8 to 9 or 16 to 18 DRAMs (Dynamic Random Access Memories) as shown in FIG. 20. Much like an SDRAM (Synchronous Dynamic Random Access Memory), each DRAM mounted in a memory module has various kinds of timing prescribed with respect to a clock signal. A SDRAM is disclosed in Japanese Patent Laid-open No. Hei5-120114.

The memory modules are arranged in a configuration shown in FIG. 21. As shown in FIG. 21, a memory riser board B0 is erected on a base board BB through a connector C0. Memory modules are provided on the memory riser board B0 in the horizontal direction at fixed intervals.

A memory controller 100 shown in FIG. 20 is provided on the base board BB shown in FIG. 21. The memory modules 10-0 to 10-7 are connected to the memory controller 100 by control lines such as a clock (CLK) line S1, an address (ADR) line S2, a data (DATA) line S3, a CS (Chip Select) line (not shown), a RAS (Row Address Strobe) line (not shown) and a CAS (Column Address Strobe) line (not shown). It should be noted that the address line S3 may include lines for providing command signals such as the chip select line, row address strobe line and the column address strobe line. Accordingly, the address line can be an address/command line.

As shown in FIG. 20, the data line S3 starting from the memory controller 100 is wired to the memory modules 10-0 to 10-7 sequentially one after another before being folded back to the memory controller 100 to form a ring-type bus. Thus, data read out from one of the memory modules 10-0 to 10-7 is propagated to the memory controller 100 through a U-shaped folded path. The wiring and the interface of the data line S3 are the same as a clock line S1 and the address/command line S2 except that only the data line S3 forms a ring-type bus.

With the memory modules 10-0 to 10-7 and the memory controller 100 having a configuration described above, in an operation to write data into the DRAM in one of the memory modules 10-0 to 10-7, a clock signal and the data are supplied to the memory module through the clock line S1 and the data line S3 respectively in addition to an address and a control signal which are fed to the memory module via the address/command line S2.

As described above, the clock line S1, the address/command line S2 and the data line S3 have the same wiring and interfaces so that signals propagated from the memory controller 100 to any of the memory modules 10-0 to 10-7 have the same waveform and an equal propagation time. As a result, the clock signal, the address signal, the control signal and the data signal are supplied to the memory module at the same phase and with the same timing, allowing the data to be written into the DRAM in the desired memory module. Also in an operation to read out data from the DRAM in one of the memory modules 10-0 to 10-7, the data can be taken in by the memory controller 100 with the same timing without regard to which memory module the data is read out from. The technique described above is referred to as a source-clock-synchronized bus system.

In addition, by arranging the memory modules 10-0 to 10-7 on the memory riser board B0 in the horizontal direction at fixed intervals and vertically erecting the memory riser board B0 on the base board BB through the connector C0 as shown in FIG. 21, a plurality of memory modules can be mounted. Furthermore, by vertically erecting the memory riser board B0 on the base board BB through the connector C0, a larger number of memory modules can be provided in comparison with a configuration wherein memory modules are mounted directly on the base board BB.

If there is a limit on the size of a box for accommodating the boards described above, then there is a corresponding limit on a height of the memory riser board B0. As a result, the number of memory modules that can be mounted on the memory riser board B0 is also limited.

Thus, according to the above, when a source-clock-synchronized bus system using a data line S3 is implemented by a piece of memory riser board B0, the number of memory modules 10 that can be connected to a data line (memory bus) is limited by the height limitation. Therefore, the memory capacity per memory bus (memory bank) is limited due to restriction on the height of the memory riser board B0. Here, a memory bank means a memory bus of one source-clock-synchronized bus.

Since the memory controller 100 is connected to the input and output of the data line S3 which is a ring-type bus wired to the memory modules, there is raised a problem that a number of terminals (pins) for the data signal are required. In particular, most of memory controllers are capable of driving a plurality of memory banks. In the case of such a memory controller, a number of terminals (pins) for as many data signals as memory banks are required for controlling the memory banks.

In order to solve the problem of the limited data storage capacity per memory bank described above, in a conventional source-clock-synchronized memory system, the clock line, the address/command line and the data line starting from the memory controller 100 are wired around the memory modules 10-0 to 10-7 mounted on a memory riser board B0 through the connector C0-1 and, then starting from the connector C0-1, further wired around the memory modules 10-8 to 10-15 mounted on another memory riser board B0 through the connector C0-2 as shown in FIG. 21 to form a ring topology with only the data line returning to the memory controller 100. In this way, the data storage capacity per memory bank can be increased. In such a conventional configuration, however, there is raised a problem that, if any of the memory riser boards B0 is pulled out from the base board BB, the connection with its connector C0 is cut off, thereby breaking the ring topology.

Further, by using the configuration described above, the length of the clock line, address/command line and the data line becomes very long thereby increasing the potential for noise on such lines. In addition the flight time of signals on the lines increases the further the memory modules are from the memory controller. This phenomena which particularly affects the data line can serve to reduce synchronization between data signals and address/command signals and reduce the speed of memory access operations. Further, due to this increasing length of the signal lines, noise on the signal lines increases.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a source-clock-synchronized memory system having a large data storage capacity per memory bank and a high mounting density resulting from the adoption of an efficient mounting technique.

It is another object of the present invention to provide a source-clock-synchronized memory system having a reduced number of terminals (pins) provided on the memory controller.

It is yet another object of the present invention to provide a source-clock-synchronized memory system allowing a plurality of memory riser boards to be connected to form a ring topology.

It is still yet another object of the present invention to provide a source-clock-synchronized memory system that shortens the length of signal lines in the memory unit thereby improving the synchronization between data and address/command signals, reducing accessing speed of the memory unit and reducing noise on the signal lines.

In order to achieve the objects of the present invention described above, the present invention provides a source-clock-synchronized memory system for use in apparatuses such as an information processing system that includes a base board, and a memory controller provided on the base board.

The source-clock-synchronized memory system includes a memory unit that is mounted on the base board. The memory unit includes a first memory riser board mounted on the base board through a first connector with a plurality of first memory modules mounted on the front surface of the first memory riser board, and a second memory riser board mounted on the base board through a second connector with a plurality of second memory modules mounted on the front surface of the second memory riser board. The first and second memory riser boards are arranged in such a way that the back surface of the first memory riser board faces the back surface of the second memory riser board. The memory unit further includes a board linking connector for connecting signal lines on the first memory riser board to corresponding signal lines on the second memory riser board.

The signal lines include clock, address/command and data lines. The signal lines start from the memory controller, pass through the first connector, are wired to the first memory modules mounted on the first memory riser board sequentially one module after another, pass through the board linking connector, and are wired to the second memory modules mounted on the second memory riser board sequentially one module after another. At least the data line further passes through the second connector and is connected back to the memory controller.

According to the source-clock-synchronized memory of the present invention as described above, the board linking connector is used for connecting signal lines on the first memory riser board to corresponding signal lines on the second memory riser board. As a result, the data storage capacity per memory bank can be increased without increasing the height of the memory riser board.

In the source-clock-synchronized memory system described above, the address/command line is ended by a matching terminator on the second memory riser board and the clock line further passes through the second connector, being connected back to the memory controller. As an alternative, the clock and address/command lines are each ended by a matching terminator on the second memory riser board.

According to one aspect of the present invention, the source-clock-synchronized memory system described above can be provided with a switch disposed on the base board. The switch connects the data line wired to the memory controller to either the data line on the first memory riser board passing through the first connector or the data line on the second memory riser board passing through the second connector in response to a control signal generated by the memory controller. Thus, data to be written into a desired memory module in the memory unit can be transferred from the memory controller to the desired memory module through the data line by way of the switch and the first connector whereas data read out from a desired memory module in the memory unit can be transferred from the desired memory module to the memory controller through the data line by way of the second connector and the switch.

In the source-clock-synchronized memory system according to the aspect of the present invention described above, the switch is actuated to connect the data line wired to the memory controller to either the data line passing through the first connector or the data line passing through the second connector so that data written into or read out from a desired memory module can propagate through the same data line wired to the memory controller. As a result, the number of terminals (pins) provided on the memory controller can be reduced.

The above-described objects of the present invention can also be achieved by providing a source-clock-synchronized memory system for use in apparatuses such as an information processing system that includes a base board, and a memory controller provided on the base board.

The source-clock-synchronized memory system includes a memory unit that is mounted on the base board. The memory unit includes a memory riser board mounted on the base board through at least a connector with a plurality of front memory modules mounted on the front surface and a plurality of back memory modules mounted on the back surface of the memory riser board.

The signal lines includes clock, address/command and data lines. The signal lines start from the memory controller, pass through the connector, are wired to the front memory modules mounted on the front surface of the first memory riser board sequentially one module after another, pass through the top of the memory riser board, and are wired to the back memory modules mounted on the back surface of the memory riser board sequentially one module after another. At least the data line further passes through the connector and is connected back to the memory controller.

The memory modules are mounted on both the front and back surfaces of a memory riser board and signal lines are stretched from the front surface of the memory riser board to the back surface thereof through the top of the board. As a result, the data storage capacity per memory bank can be increased without increasing the height of the memory riser board and without increasing the number of components such as connectors.

According to another aspect of the present invention, there is provided a source-clock-synchronized memory system for use in apparatuses such as an information processing system that includes a base board, and a memory controller provided on the base board.

The source-clock-synchronized memory system includes a memory unit that is mounted on the base board. The memory unit includes a memory riser board mounted on the base board through at least a connector with a plurality of memory modules mounted on the front and back surfaces of the memory riser board and a switch provided on the memory riser board for connecting a data line wired to the connector to one of two data lines wired to the modules in response to a control signal output by the memory controller.

Signal lines including clock and address/command lines start from the memory controller, pass through the connector and are wired to the memory modules mounted on the front and back surfaces of the memory riser board sequentially one module after another. A data line including the data line wired to the connector and the two data lines wired to the memory modules starts from the memory controller, passes through the connector and the switch, is wired to the memory modules mounted on the front and back surfaces of the memory riser board sequentially one module after another, passes through the switch again and is folded back to the memory controller.

A modification of the source-clock-synchronized memory system described above can be provided where the memory controller and the memory unit are provided on the base board.

The memory unit can be configured to include a first memory riser board mounted on the base board through a first connector with a plurality of first memory modules mounted on the front surface of the first memory riser board, and a second memory riser board mounted on the base board through a second connector with a plurality of second memory modules mounted on the front surface of the second memory riser board. The first and second memory riser boards are arranged in such a way that the back surface of the first memory riser board faces the back surface of the second memory riser board. The memory unit further includes a board linking connector for connecting signal lines on the first memory riser board to corresponding signal lines on the second memory riser board.

The signal lines includes clock, address/command and data lines. The signal lines start from contact points on the first connector, are wired to the first memory modules mounted on the first memory riser board sequentially one module after another, pass through the board linking connector, and are wired to the second memory modules mounted on the second memory riser board sequentially one module after another. At least the data line is further extended to another contact point on the second connector.

As an alternative, the memory unit c