Non-oxidizing touch contact interconnect for semiconductor test systems and method of fabrication

Claims

What is claimed is:

1. A method for fabricating an interconnect for testing a semiconductor component having a contact comprising:

providing a substrate;

forming a contact member on the substrate configured for contacting the contact on the component;

forming a conductive layer on the contact member;

electrolessly depositing a barrier layer on the conductive layer comprising a first material configured to prevent diffusion of the conductive layer; and

electrolessly depositing a non-oxidizing layer on the barrier layer comprising a second material configured to provide a touch surface on the contact member for making a temporary electrical connection with the contact on the component.

2. The method of claim 1 further comprising forming a conductor and a bonding pad on the substrate in electrical communication with the conductive layer and electrolessly depositing the non-oxidizing layer on the bonding pad to provide a wire bondable surface.

3. The method of claim 1 wherein the first material comprises a material selected from the group consisting of nickel, zinc, chromium and palladium.

4. The method of claim 1 wherein the second material comprises a material selected from the group consisting of palladium, gold, tungsten, platinum, gold-platinum, silver-palladium, silver-platinum and palladium-gold.

5. A method for fabricating an interconnect for testing a semiconductor component having a contact comprising:

providing a substrate;

forming a contact member on the substrate comprising a pillar configured for contacting the contact on the component;

depositing a conductive layer on the pillar and on the substrate;

patterning and etching the conductive layer leaving the pillar at least partially covered with a portion of the conductive layer, and forming a conductor and a bonding pad in electrical communication with the portion;

electrolessly depositing a barrier layer on the conductive layer comprising a first material configured to prevent diffusion of the conductive layer; and

electrolessly depositing a non-oxidizing layer on the barrier layer comprising a second material configured to provide a touch surface on the contact member for making a temporary electrical connection with the contact on the component and a wire bondable surface on the bonding pad for wire bonding to the interconnect.

6. The method of claim 5 wherein the pillar comprises a projection configured to penetrate the contact on the component.

7. The method of claim 5 wherein the first material comprises a material selected from the group consisting of nickel, zinc, chromium and palladium.

8. The method of claim 5 wherein the second material comprises a material selected from the group consisting of palladium, gold, tungsten, platinum, gold-platinum, silver-palladium, silver-platinum, palladium-gold and nickel-cobalt.

9. The method of claim 5 further comprising forming a projection on the pillar configured to penetrate the contact to a limited penetration depth.

10. A method for fabricating an interconnect for testing a semiconductor component having a contact bump comprising:

providing a substrate;

forming a contact member on the substrate comprising an indentation configured to retain the contact bump;

electrolessly depositing a barrier layer on the conductive layer comprising a first material configured to prevent diffusion of the conductive layer; and

electrolessly depositing a non-oxidizing layer on the barrier layer comprising a second material configured to provide a touch surface on the contact member for making a temporary electrical connection with the contact bump on the component.

11. The method of claim 10 further comprising forming a conductor and a bonding pad on the substrate in electrical communication with the conductive layer and electrolessly depositing the non-oxidizing layer on the bonding pad to provide a wire bondable surface.

12. The method of claim 10 wherein the first material comprises a material selected from the group consisting of nickel, zinc, chromium and palladium.

13. The method of claim 10 wherein the second material comprises a material selected from the group consisting of palladium, gold, tungsten, platinum, gold-platinum, silver-palladium, silver-platinum, palladium-gold and nickel-cobalt.

14. The method of claim 10 wherein the indentation comprises a stepped surface with an edge configured to penetrate the contact bump.

15. A method for fabricating an interconnect for testing a semiconductor component having a contact comprising:

providing a substrate;

forming a contact member on the substrate configured for contacting the contact on the component and comprising a conductive layer;

electrolessly depositing a barrier layer on the conductive layer by submerging the substrate in a first solution, the barrier layer comprising a first material configured to prevent diffusion of the conductive layer; and

electrolessly depositing a non-oxidizing layer on the barrier layer by submerging the substrate in a second solution, the non-oxidizing layer comprising a second material configured to provide a touch surface on the contact member for making a temporary electrical connection with the contact on the component.

16. The method of claim 15 wherein the first material comprises nickel and the second material comprises palladium.

17. The method of claim 15 further comprising forming a conductor on the substrate in electrical communication with the conductive layer.

18. The method of claim 17 further comprising electrolessly depositing the non-oxidizing layer on the conductor to provide a wire bonding surface.

19. The method of claim 15 wherein the contact member comprises a pillar comprising a portion of the substrate.

20. The method of claim 15 wherein the contact member comprises an indentation in the substrate configured to retain the contact.

21. The method of claim 15 wherein the contact member comprises a stepped indentation in the substrate comprising an edge configured to penetrate the contact.

22. The method of claim 15 wherein the first solution comprises nickel chloride, sodium hydroxyacetate, and sodium hypophosphate.

23. The method of claim 15 wherein the second solution comprises palladium chloride and sodium hypophosphate.

24. An interconnect for testing a semiconductor component having a contact comprising:

a substrate;

a contact member on the substrate configured to electrically engage a contact on the component and comprising a conductive layer;

a barrier layer on the conductive layer comprising a first material configured to prevent diffusion of the conductive layer and provide an adhesive surface; and

a non-oxidizing layer on the barrier layer comprising a second material configured to provide a touch surface on the contact member for making a temporary electrical connection with the contact on the component.

25. The interconnect of claim 24 further comprising a bonding pad on the substrate in electrical communication with the conductive layer and at least partially covered by the barrier layer and the bonding layer.

26. The interconnect of claim 24 further comprising a conductor in electrical communication with the conductive layer and at least partially covered by the barrier layer and the bonding layer.

27. The interconnect of claim 24 wherein the contact member comprises a pillar on the substrate at least partially covered by the conductive layer.

28. The interconnect of claim 24 wherein the contact member comprises an indentation in the substrate at least partially covered by the conductive layer.

29. An interconnect for testing a semiconductor component having a contact comprising:

a substrate;

a contact member on the substrate configured for contacting the contact on the component;

a conductive layer on the substrate and the contact member comprising a portion at least partially covering the contact member, a conductor configured to provide an electrical path to the contact member, and a bonding pad, and

a non-oxidizing layer on the conductive layer comprising a metal configured to provide a touch surface on the contact member for making a temporary electrical connection with the contact on the component, and a wire bondable surface on the bonding pad for wire bonding to the interconnect.

30. The interconnect of claim 29 further comprising a barrier layer between the conductive layer and the non-oxidizing layer comprising a material selected from the group consisting of nickel, zinc, chromium and palladium.

31. The interconnect of claim 29 wherein the metal comprises a material selected from the group consisting of palladium, gold, tungsten, platinum, gold-platinum, silver-palladium, silver-platinum, palladium-gold and nickel-cobalt.

32. The interconnect of claim 29 wherein the contact member comprises a raised pillar with at least one projection configured to penetrate the contact.

33. The interconnect of claim 29 wherein the contact member comprises an indentation configured to retain the contact.

34. The interconnect of claim 29 wherein the contact member comprises a stepped indentation with an edge configured to penetrate the contact.

35. An interconnect for testing a semiconductor component having a contact bump comprising:

a substrate;

a contact member on the substrate comprising an indentation configured to retain and electrically engage the contact bump;

a conductive layer on the substrate and the contact member covering at least a portion of the indentation and defining a conductor for providing an electrical path to the contact member, and a bonding pad for the conductor; and

a non-oxidizing layer on the conductive layer comprising a metal configured to provide a touch surface on the contact member for making a temporary electrical connection with the contact bump on the component, and a wire bondable surface on the bonding pad.

36. The interconnect of claim 35 wherein the indentation comprises an inverted pyramid with an edge configured to penetrate the contact bump.

37. The interconnect of claim 35 wherein the non-oxidizing layer comprises a material selected from the group consisting of palladium, gold, tungsten, platinum, gold-platinum, silver-palladium, silver-platinum, palladium-gold and nickel-cobalt.

38. The interconnect of claim 35 wherein the substrate comprises a stepped edge wherein the bonding pad is located.

39. An interconnect for testing a semiconductor component having a contact comprising:

a substrate;

a contact member on the substrate comprising a pillar and a penetrating projection configured to penetrate the contact on the component to a limited penetration depth;

a conductive layer on the substrate covering the projection and at least a portion of the pillar, and defining a conductor for the contact member and a bonding pad for the conductor;

a barrier layer on the conductive layer comprising a first material configured to prevent diffusion of the conductive layer; and

a non-oxidizing layer on the barrier layer comprising a second material configured to provide a touch surface on the contact member for making a temporary electrical connection with the contact on the component.

40. The interconnect of claim 39 wherein the non-oxidizing layer comprises a material selected from the group consisting of palladium, gold, tungsten, platinum, gold-platinum, silver-palladium, silver-platinum, palladium-gold and nickel-cobalt.

41. The interconnect of claim 39 wherein the substrate comprises a stepped edge wherein the bonding pad is located.

42. A system for testing a semiconductor component having a contact comprising:

test circuitry;

a carrier configured to contain the component comprising an external contact in electrical communication with the test circuitry; and

an interconnect on the carrier comprising:

a substrate

a contact member on the substrate configured to electrically engage the contact on the component;

a conductive layer on the substrate and the contact member comprising a conductor in electrical communication with the external contact;

a barrier layer on the conductive layer comprising a first material configured to prevent diffusion of the conductive layer; and

a non-oxidizing layer on the barrier layer comprising a second material configured to provide a touch surface on the contact member for making a temporary electrical connection with the contact on the component.

43. The system of claim 42 wherein the second material comprises a material selected from the group consisting of palladium, gold, tungsten, platinum, gold-platinum, silver-palladium, silver-platinum and palladium-gold.

44. The system of claim 42 wherein the component comprises an element selected from the group consisting of bare dice and chip scale packages.

45. A system for testing a semiconductor wafer having a contact comprising:

test circuitry;

a wafer handler in electrical communication with the test circuitry; and

an interconnect on the wafer handler comprising:

a substrate

a contact member on the substrate configured to electrically engage the contact on the wafer;

a conductive layer on the substrate and the contact member comprising a conductor in electrical communication with the test circuitry;

a barrier layer on the conductive layer comprising a first material configured to prevent diffusion of the conductive layer; and

a non-oxidizing layer on the barrier layer comprising a second material configured to provide a touch surface on the contact member for making a temporary electrical connection with the contact on the component.

46. The system of claim 45 wherein the second material comprises a material selected from the group consisting of palladium, gold, tungsten, platinum, gold-platinum, silver-palladium, silver-platinum, palladium-gold and nickel-cobalt.

47. The system of claim 45 further comprising a flex circuit bonded to the conductor and to a bonding site on the wafer handler.

FIELD OF THE INVENTION

This invention relates to interconnects for testing semiconductor components, such as semiconductor wafers, singulated dice and chip scale packages. In addition, this invention relates to a method for fabricating interconnects and to test systems employing interconnects.

BACKGROUND OF THE INVENTION

Semiconductor components, such as wafers, singulated dice, and chip scale packages must be tested and burned-in prior to use in multi chip modules and other electronic devices. For performing these test procedures, temporary electrical connections can be made to contacts on the components. Test signals can then be transmitted through the temporary electrical connections to the integrated circuits contained on the components. For wafers and singulated dice, the contacts typically comprise aluminum bond pads, or alternately solder bumps. For chip scale packages the contacts typically comprise solder bumps.

The temporary electrical connections can be made to the contacts on the components using an interconnect. The interconnect includes contact members configured to electrically engage the contacts on the components. U.S. Pat. No. 5,483,741 to Akram et al. describes an exemplary interconnect for singulated dice. The '741 interconnect includes a silicon substrate with raised contact members covered with a metal silicide layer.

One aspect of these interconnects is that the contact members must be capable of forming low resistance, or "ohmic", electrical connections with the contacts on the components. Typically, the contacts on the components include a native oxide layer (e.g., aluminum oxide) that must be penetrated to electrically contact the underlying metal.

However, the contact members on the interconnect can also include native oxide layers that can affect the electrical characteristics of the temporary electrical connections with the components being tested. For example, metal silicide contact members are subject to oxidation, which increases the electrical resistivity of the temporary electrical connections with the components. The electrical resistivity of the temporary electrical connections is also a function of the resistivity of the materials which form the contact members. It would be desirable to be able to form the contact members on interconnects with non-oxidizing, low-resistivity materials.

Another aspect of interconnects used for testing semiconductor components is that electrical paths must be made between the contact members on the interconnects, and external test circuitry. These electrical paths sometimes include wire bonds. If the contact members are formed of a material, such as a metal silicide, that cannot be easily wire bonded, then additional layers must be added to the interconnect to provide wire bonding sites. It would be desirable to be able to form the contact members on interconnects with wire-bondable materials.

In view of the foregoing, the present invention is directed to an improved interconnect having contact members covered with a non-oxidizing, wire bondable layer.

SUMMARY OF THE INVENTION

In accordance with the present invention, an improved interconnect for testing semiconductor components, a method for fabricating the interconnect, and test systems employing the interconnect, are provided. The interconnect includes a substrate with patterns of contact members for contacting the component. The contact members can be configured for contacting planar contacts on the components (e.g., bondpads, test pads), or alternately, can be configured for contacting contact bumps on the components (e.g., solder bumps). In addition to the contact members, the interconnect includes patterns of conductors formed on the substrate in electrical communication with the contact members. The conductors can include bonding pads for forming bonded electrical connections, such as wire bonds, or solder bonds, between the interconnect and a test apparatus adapted to apply test signals to the components.

The interconnect also includes an electrolessly deposited non-oxidizing layer covering the contact members, conductors and bonding pads. Preferred materials for the non-oxidizing layer include palladium, gold, tungsten, platinum, gold-platinum, silver-palladium, silver-platinum, palladium-gold and nickel-cobalt. On the contact members, the non-oxidizing layer forms a low resistivity "touch" surface for electrically contacting the contacts on the components. On the bonding pads, the non-oxidizing layer is wire bondable and solderable, which permits bonded connections to be made to the bonding pads.

The method for fabricating the interconnect, simply stated, includes the steps of: providing the substrate; forming the contact members on the substrate; depositing and patterning a conductive layer on the contact members and substrate to form conductors and bonding pads for the contact members; and then electrolessly depositing a barrier layer, and a non-oxidizing layer on the patterned conductive layer.

Different embodiments of contact members are provided for electrically contacting different types of contacts on the components. For contacting planar contacts, such as aluminum bond pads, the contact members can comprise raised pillars and penetrating projections covered with the conductive layer. For contacting contact bumps, such as solder bumps, the contact members can comprise indentations covered with the conductive layer. The indentations can include a stepped edge for penetrating the contact bumps and can be shaped to prevent excessive deformation of the contact bumps.

In the illustrative embodiments the conductive layer can be a highly conductive metal, such as copper or aluminum, formed using a suitable metallization process (e.g., deposition, patterning, etching). Following formation thereof, the conductive layer can be cleaned and activated in a zincate solution. Next, the barrier layer can be electrolessly deposited on the conductive layer. Preferred materials for the barrier layer include nickel, zinc, chromium, and palladium. Following electroless deposition of the barrier layer, the non-oxidizing layer can be electrolessly deposited on the barrier layer. During formation of the barrier and non-oxidizing layers, masks are not required, as plating to the exposed conductive layer is automatic.

The completed interconnect can be used in a die level test system for testing singulated dice and chip scale packages, or in a wafer level system for testing dice contained on a semiconductor wafer. In the die level system, the interconnect can be mounted to a test carrier configured to contain the dice or chip scale packages. In the wafer level system, the interconnect can be wafer-sized and configured for mounting to a wafer handler in place of a conventional probe card.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic perspective view of an interconnect constructed in accordance with the invention;

FIGS. 2A-2E are enlarged schematic cross sectional views taken along section line 2A-E-2A--E of FIG. 1, illustrating different embodiment contact members of the interconnect, in