A system and method for reducing linearity errors in an A/D converter, such as a delta-sigma converter. The linearity errors in the delta-sigma converter are modeled by generating a set of digital signals representative of an inputted sine wave. The set of digital signals are low-pass filtered and subjected to a fast Fourier transform algorithm to generate a frequency domain representation of the sine wave. Thereafter, a net linearity error spectrum is removed from the frequency domain representation and inverse Fourier transform back into the time domain. The filtered set of digital signals are also sorted into subsets of digital signals where each signal in a subset corresponds to a particular output of a delta-sigma modulator contained within the delta-sigma converter. A fast Fourier transform algorithm is applied to each of the filtered subsets of digital signals to generate a frequency domain representation thereof. Specific linearity errors are generated by applying an inverse Fourier transform algorithm to each of the specific linearity error spectrums in the frequency domain representations of the filtered subsets of digital signals. Thereafter, linearity error correction coefficients are generated as a function of the net linearity error and the specific linearity errors. The linearity error correction coefficients are used to generate entries in a look-up table where the entries are adjustable by digital outputs of the delta-sigma modulator. The look-up table is used to correct digital signals outputted by the delta-sigma modulator prior to decimation and digital filter.
CONTINUATION DATA
This is a continuation-in-part of application Ser. No. 09/105,283 titled "System and Method for Generating a Sigma-Delta Correction Circuit" and filed Jun. 26, 1998 (Atty. Docket No. 5150-16501), whose inventor was Niels Knudsen, which is a continuation-in-part of application Ser. No. 08/772,785 titled "System and Method for Generating a Sigma-Delta Correction Circuit" and filed Dec. 23, 1996 (Atty. Docket No. 5150-16500), which issued as U.S. Pat. No. 5,781,138, and whose inventor was Niels Knudsen.
This is also a continuation-in-part of application Ser. No. 09/105,847 titled "System and Method for Reducing Errors in a Delta Sigma Converter" and filed Jun. 6, 1998 (Atty. Docket No. 5150-15201), whose inventor was Niels Knudsen, which is a continuation-in-part of application Ser. No. 08/771,480 titled "System and Method for Reducing Errors in a Delta Sigma Converter" and filed Dec. 23, 1996 (Atty. Docket No. 5150-15200), which issued as U.S. Pat. No. 5,781,137, and whose inventor was Niels Knudsen.
This is also a continuation-in-part of application Ser. No. 09/186,314 titled "System and Method for Generating a Sigma-Delta Correction Circuit Using Matrix Calculation of Linearity Error Correction Coefficients" and filed on Nov. 4, 1998, whose inventors were Niels Knudsen and Mark Whittington.
A method corrects the error in an output digital signal (Out) of an analog/digital converter (ADC) (100), in which the error is introduced by a multibit digital/analog converter (DAC) (125) incorporated in the ADC. The method calculates (905) coefficients (p.sub.i,p.sub.i r.sub.i) of a linear combination of vectors of a vector space representative of the error introduced by the DAC; calculates (910-1, . . . , 910-7) the correlation of a signal (Res1d) containing the error introduced by the DAC, to extract an estimation of each vector; calculates a linear combination representative of the estimation of the error introduced by the DAC, and uses the estimation of the error introduced by the DAC to correct the ADC output signal.
A system and method for calibrating an analog to digital (A/D) converter. The A/D converter includes an internal D/A converter, wherein the internal D/A converter includes a plurality of current generators, and wherein one or more of the current generators may produce linearity errors in the A/D converter. The A/D converter includes a switching element connected to the internal D/A converter. During calibration, the switching element operates to adjust connections to the current generators in the internal D/A converter one or more times according to different switching patterns, thereby causing different ones of the current generators to be stimulated by an input to the A/D converter. This avoids the necessity of using a complex and costly waveform generator input during calibration, which would normally be required to ensure that all of the current generators in the internal D/A converter are stimulated. Rather, a much simpler input can be used in calibrating the A/D converter, thereby reducing cost. A plurality of output digital signals from the A/D converter are recorded during calibration, wherein these recorded signals contain linearity error information associated with the respective current generators. This linearity error information may be extracted and used in calibrating the A/D converter.
In an A/D conversion control apparatus for use in an electronic controller such as an engine ECU of a vehicle, each of successive sets of A/D converted values of an analog signal (each set comprising 3 or more values) is processed to obtain a median value of the set, and the median values are subjected to digital smoothing processing to obtain successive final result values, with effects of noise contained in the analog signal being effectively excluded. The final result values are suitable as control data, supplied to a control device such as a microcomputer of an ECU.
An analog to digital (A/D) converter which includes A/D converter and D/A converter modes. The A/D converter includes an internal digital to analog (D/A) converter (DAC) that may be used in a feedback loop during A/D operations (in the A/D mode), and may be used as a stand-alone D/A converter in the D/A mode. The present invention also takes advantage of advanced calibration techniques available for the internal D/A converter of the A/D converter. A processing unit may be coupled to the output of the internal A/D converter. The processing unit or a separate computer system may perform a calibration function in the A/D mode to generate linearity error correction information for correcting linearity errors in the internal D/A converter. The linearity error correction information may be used in configuring a linearity error correction device implemented by the processing unit. In the A/D mode, the processing unit may implement linearity error correction and a decimation function during A/D conversion. In the D/A mode, the processing unit also may implement linearity error correction functions as well as other functions during D/A conversion. The A/D converter may also include switching elements used in configuring the A/D converter in either the A/D mode or the D/A mode.
