Integrated circuit having memory which synchronously samples information with respect to external clock signals

Claims

What is claimed is:

1. A synchronous memory device, wherein the memory device includes at least one memory section having a plurality of memory cells, the memory device comprising:

clock receiver circuitry to receive an external clock signal from an external bus;

clock generation circuitry coupled to the clock receiver circuitry, wherein the clock generation circuitry includes a delay locked loop to generate a first internal clock signal; and

input receiver circuitry, coupled to the clock generation circuitry and the external bus, to sample information from the external bus in response to the first internal clock signal.

2. The memory device of claim 1 wherein the information is included in a request packet.

3. The memory device of claim 1, wherein the clock generation circuit further generates a second internal clock signal which is synchronized with the external clock signal and the input receiver further includes:

a first input latch to sample first information synchronously with respect to an edge of the first internal clock signal; and

a second input latch to sample second information synchronously with respect to an edge of the second internal clock signal.

4. The memory device of claim 3, wherein the first and second internal clock signals are complementary signals.

5. The memory device of claim 1, further including:

second clock generation circuitry coupled to the clock receiver circuitry, wherein the second clock generation circuitry includes a delay locked loop to generate a second internal clock signal; and

wherein the input receiver circuitry includes:

a first input latch to sample first information synchronously with respect to a clock edge of the first internal clock signal; and

a second input latch to sample second information synchronously with respect to a clock edge of the second internal clock signal.

6. The memory device of claim 5 wherein the clock edge of the first internal clock signal is a rising edge transition and the clock edge of the second internal clock signal is a rising edge transition.

7. The memory device of claim 1 wherein the external clock signal has a low voltage swing and the first internal clock signal has a full logic swing.

8. An integrated circuit having at least one memory section including a plurality of memory cells, the integrated circuit comprising:

clock receiver circuitry to receive an external clock signal from an external bus;

clock generation circuitry coupled to clock receiver circuitry to receive the external clock signal and to generate a first internal clock signal and a second internal clock signal, wherein the clock generation circuitry includes a delay locked loop to generate the first internal clock signal; and

input receiver circuitry, coupled to the external bus and the clock generation circuitry, to sample information from the external bus in response to the first and second internal clock signals.

9. The integrated circuit of claim 8, wherein the input receiver circuitry includes:

a first input latch to latch first information synchronously with respect to an edge of the first internal clock signal; and

a second input latch to latch second information synchronously with respect to an edge of the second internal clock signal.

10. The integrated circuit of claim 9 wherein the first internal clock signal is complementary to the second internal clock signal, the edge of the first internal clock signal is a rising edge, and the edge of the second internal clock signal is a rising edge.

11. The integrated circuit of claim 9 wherein the first and second information are included in a request packet.

12. The integrated circuit of claim 11, wherein the first and second information are included in the same request packet.

13. The integrated circuit of claim 8 wherein the clock generation circuitry includes a second delay locked loop to generate the second internal clock signal.

14. A synchronous memory device having at least one memory section including a plurality of memory cells, the memory device comprising:

clock receiver circuitry to receive a first and a second external clock signal from an external bus; and

input receiver circuitry, coupled to the clock receiver circuitry and the external bus, to sample information on the external bus synchronously with respect to the first and second external clock signals.

15. The memory device of claim 14, further including:

a clock generation circuit, coupled to the clock receiver circuitry, to generate a first internal clock signal which is synchronized with the first and second external clock signals; and

wherein the input receiver circuitry samples information on the external bus in response to the first internal clock signal.

16. The memory device of claim 15 wherein the input receiver circuitry samples first information synchronously with respect to the first and second external clock signals and wherein the first information is included in a request packet.

17. The memory device of claim 15 wherein the clock generation circuit generates the first internal clock signal using a delay locked loop.

18. The memory device of claim 14, further including:

a clock generation circuit, coupled to the clock receiver circuitry, to generate first and second internal clock signal; and

wherein the input receiver circuitry samples first information on the external bus in response to the first internal clock signal and samples second information on the external bus in response to the second internal clock signal.

19. The memory device of claim 18 wherein the input receiver circuitry samples first information synchronously with respect to a rising edge of the first external clock signal and samples second information synchronously with respect to a falling edge of the first external clock signal.

20. The memory device of claim 18 wherein the input receiver further includes:

a first input latch coupled to the first internal clock signal, wherein the first input latch latches first information in response to a rising edge of the first internal clock signal; and

a second input latch coupled to the second internal clock signal, wherein the second input latch latches second information in response to a rising edge of the second internal clock signal.

21. The memory device of claim 20 wherein a clock transition edge of the second internal clock signal occurs between a rising edge of the first external clock signal and a rising edge of the second external clock signal, and the second internal clock signal is complementary to the first internal clock signal.

22. The memory device of claim 20 wherein the first internal clock signal is complementary to the second internal clock signal.

23. The memory device of claim 20 further including:

a first clock generation circuit, coupled to the clock receiver circuitry, to generate a first internal clock signal which is synchronized with the first external clock signal;

a second clock generation circuit, coupled to the clock receiver circuitry, to generate a second internal clock signal which is synchronized with the second external clock signal; and

wherein the input receiver further includes:

a first input latch to latch first information in response to a transition of the first internal clock signal; and

a second input latch to latch second information in response to a transition of the second internal clock signal.

24. The memory device of claim 23 wherein the transition of the first internal clock signal is a rising edge transition and the transition of the second internal clock signal is a rising edge transition.

25. The memory device of claim 23 wherein the first clock generation circuit includes a first delay locked loop, and the second clock generation circuit includes a second delay locked loop.

26. An integrated circuit having at least one memory section including a plurality of memory cells, the integrated circuit comprising:

clock receive circuitry to receive a first and second external clock signal from a bus;

clock generation circuit