A diode is formed by forming a PN junction region 6 with a p region 5 formed on a buried oxide film 19 side and an n region 7 formed on the surface side in a surface silicon layer 3 which is isolated by the buried oxide film 19 of an SOI substrate 1, providing a lightly doped p region 33 on one end side of the PN junction region 6 and a lightly doped n region 31 on an other end side, forming a heavily doped p region 13 and a heavily doped n region 9 at the respective surface portions of the lightly doped p region 33 and the lightly doped n region 31 in such a manner as not to contact the PN junction region 6, and providing two metal plates which respectively connect to the heavily doped p region 13 and the heavily doped n region 9.
A circuit that includes an isolation boundary formed to a depth in a substrate defining an active area of the substrate, a primary junction formed in the active area to a primary junction depth in the substrate to collect electron/hole pairs, and a secondary junction formed in the active area adjacent to the isolation boundary to a secondary junction depth at least equal to the isolation boundary depth.
A device is provided which includes a single-crystal semiconductor region disposed in a substrate. The single-crystal region includes a first semiconductor material and a diode disposed in the single-crystal region. The diode includes an anode region including a first alloy region, being an alloy of the first semiconductor material with a second semiconductor material, and a second region which consists essentially of the first semiconductor material, the diode further including a cathode region.
A combination of a thin-film .mu.c-Si and a-Si:H containing diode structure characterized by an ultra-high current density that exceeds 1000 A/cm.sup.2, comprising: a substrate; a bottom metal layer disposed on the substrate; an n-layer of .mu.c-Si deposited the bottom metal layer; an i-layer of .mu.c-Si deposited on the n-layer; a buffer layer of a-Si:H deposited on the i-layer, a p-layer of .mu.c-Si deposited on the buffer layer; and a top metal layer deposited on the p-layer.
An implant-free enhancement mode metal-oxide semiconductor field effect transistor (EMOSFET) is provided. The EMOSFET has a III-V compound semiconductor substrate and an epitaxial layer structure overlying the III-V compound semiconductor substrate. The epitaxial material layer has a channel layer and at least one doped layer. A gate oxide layer overlies the epitaxial layer structure. The EMOSFET further includes a metal gate electrode overlying the gate oxide layer and source and drain ohmic contacts overlying the epitaxial layer structure.
An optical waveguide structure (10) is provided. The optical waveguide structure (10) has a monocrystalline substrate (12), an amorphous interface layer (14) overlying the monocrystalline substrate (12) and an accommodating buffer layer (16) overlying the amorphous interface layer (14). An optical waveguide layer (20) overlies the accommodating buffer layer (16).
