A simulation executing unit includes a conversion unit and a simulation portion. The conversion unit includes a circuit dividing portion, a circuit converting portion and a converted logic circuit generating portion, and the circuit dividing portion divides a logic circuit into combinational partial circuits each interposed between registers or between a register and an input pin or the like. The circuit converting portion generates, on the basis of the divided combinational partial circuits, a converted logic circuit by modifying allocation of registers included in the logic circuit, so as to decrease the number of registers included in the logic circuit without changing the output timing of the logic circuit. The simulation unit performs a simulation on the converted logic circuit.
A high-level synthesis device includes: a process extraction section for extracting an available process which performs data communications through a path having no loop from all processes described in an inputted behavioral description; a circuit synthesis section for producing partial circuits realizing the respective available processes and connecting the partial circuits in accordance with the inputted behavioral description so as to synthesize a circuit; and a delay insertion section for inserting a delay circuit in a path connecting partial circuits realizing the available processes so that data communications between the partial circuits through a plurality of paths are synchronized with each other. With the high-level synthesis device, it is possible to simulate synchronous communications between asynchronous processes in accordance with the inputted behavioral description including the description of the synchronous communications, and synthesize a circuit which has a small scale on the whole and operates at a high speed without providing control lines for handshaking.
In order to efficiently create a library of characteristic values of a low hierarchical circuit, which library is used in operation verification of circuitry including low hierarchical circuitry and high hierarchical circuitry, so that the time period necessary to create a library is considerably reduced, the present apparatus includes a recognizing unit which recognizes a simulation object circuit in circuitry; a simulation unit which simulates the simulation object circuit; and a creating unit which creates a library of characteristic values of the simulation object circuit based on the simulation result obtained by said simulation unit.
An analysis of a circuit to be analyzed is made in correspondence with the name of each element which includes a cell configuring the circuit to be analyzed, and the meaning or the relationship of a signal to a terminal of each element, and a determination of whether or not a path from a starting point to an end point is a multi-cycle path is made by using a result of the analysis, thereby providing an analyzing method that can also cope with the use of a gated clock, and an increase in the scale of a circuit, has a short processing time, and can accurately detect a multi-cycle path.
