A race-free shift register device having a plurality of series-connected flip-flop circuits and latch circuits. By a delay circuit, the timing of a clock signal input to each individual flip-flop circuit is delayed with respect to the clock signal input to the associated latch circuit, so that the operating timing of the latch circuit is not delayed with respect to the operating timing of the flip-flop circuit, even if a skew happens to occur in the clock signal. The latch circuit therefore surely holds bit data output by the flip-flop circuit, so the bit data to be input to a preceding flip-flop circuit is prevented from being prematurely provided to a succeeding flip-flop circuit, thereby ensuring prevention of a race condition.
A shift register device includes transistor pass gates and latches connected in series and disposed along a data bit line, each latch connected to a corresponding transistor pass gate. Each transistor pass gate is controlled by a separate control signal input line that a provides a signal to the transistor pass gate connected to it. The signals are provided in a staggered time pattern beginning with a latch disposed last in succession, shifting data from one position to the next succeeding position. Each latch is capable of storing one bit of data. The shift register utilizes less silicon space while reducing the amount of power consumed during operation.
Methods and apparatus for controlling critical races in sequential circuits so that the there are no conflicts when two or more different data signals exists on shared circuit paths. This enables the design and implementation of sequential circuits having fewer gates than conventional circuit designs of equivalent function that translates into smaller area and power consumption. The control of the critical race is accomplished by adjusting the relative delay of the individual sections of one or more loops.
