A programmable shift register in which the length (e.g., number of bits), number and location of taps, operating mode (i.e., counting up/down) and number of skip states are configured by programming selected memory cells. The programmable shift register includes a plurality of flip-flops, a programmable interconnect circuit, a next-state control circuit and a mode control circuit. The output terminal of each flip-flop drives a different bus line in the programmable interconnect circuit. Each bus line is programmably connected to a plurality of I/O lines via programmable interconnect points (PIPs). At least two of the second lines are connected to the input terminal of each flip-flop via portions (e.g., multiplexers) of the mode control circuit. Programming the PIPs to link selected flip-flop input and output terminals forms one or more shift registers of a selected length. The mode control circuit is programmable such that the shift register loads an initial operating state, or to implements bi-directional (count up/down) control. Some of the I/O lines of the programmable interconnect circuit are connected to the next-state control circuit. The next-state control circuit includes a sequence circuit, a maximal count circuit and a skip-state circuit, all of which are programmable to utilize the output signals from the flip-flops that are transmitted on the first bus.
A multi-shifting shift register is adapted for outputting a selected address signal to a memory unit, and includes a control circuit for outputting a number (i) of shift signals and a timing pulse signal. One of the shift signals is at an enabled state and the other ones of the shift signals are at a disabled state during each cycle of the timing pulse signal. A multi-shifting circuit includes a number (N), which is larger than the number (i), of cascaded register units, each of which has a flip-flop that has an input end, and an output end for generating an address signal, and a selector that has the number (i) of select inputs for receiving the number (i) of the shift signals respectively from the control circuit, the number (i) of address signal inputs, and an output. The output end of the flip-flop is connected to a first one of the address signal inputs of the selector. The input end of the flip-flop of each of the register units is connected to the output of the selector of a preceding one of the register units. A j.sup.th one of the address signal inputs of the selector of each of the registers units is connected to the output end of the flip-flop of a (j-1).sup.th preceding one of the register units. The number (j) is a number between 2 and i. The selected address signal is the address signal that is outputted by the flip-flop of one of the register units and that is at the enabled state.
A circuit, which shifts an M-sequence code with an arbitrary number of bits, is realized by a small circuit scale. D-type flip-flops 1-6 form a shift register for generating an M-sequence and having outputs d.sub.0 -d.sub.5 of respective stages, to which 2.sup.5 bit shift inserting circuit 10 is connected in the manner of receiving the outputs d.sub.0 -d.sub.5 as respective inputs and of outputting outputs O.sub.0 -O.sub.5, to which 2.sup.4 bit shift inserting circuit 11 is connected in the manner of receiving the outputs O.sub.0 -O.sub.5 as respective inputs. In the same manner, a 2.sup.3 bit shift inserting circuit 12, a 2.sup.2 bit shift inserting circuit 13, a 2.sup.1 bit shift inserting circuit 14, and a 2.sup.0 bit shift inserting circuit 15 are sequentially connected with one another. Each of bit shift inserting circuits 10-15 respectively shifts a predetermined bit when control signals b.sub.5 -b.sub.0 are "1", and does not shift a bit when "0" so as to output an input as it is. Therefore, it is possible to obtain an arbitrary bit shift.
A bi-directional shift register circuit comprising, a plurality of shift register stages, each having an input and an output terminal, and a bi-directional shift controller circuit associated with each of said shift register stages is disclosed. The bi-directional shift controller circuit comprises a first input connected to a output terminal of a first shift register stage and a second input connected to a output terminal of a second shift register stage. Means to apply a first and a second control voltage, wherein said first and second control voltage are different, and a combinatorial circuit responsive to said first and second control voltages to apply an indication of an input received from either said first shift register or said second shift register to said corresponding shift register input terminal. The combinatorial circuit configuration is that of a NOR gate or a NAND gate.
A clock divider circuit for generating an output clock signal derived from an input clock signal with the output clock signal having a selected frequency and duty cycle. The clock divider circuit comprises a linear shift register with a feedback loop. Data is shifted through the stages of the linear shift register in response to the input clock signal being applied at a clock input port. The output clock signal is derived from the data outputs on selected stages in the linear shift register. In one aspect, the clock divider circuit divides a 667 MHz input clock signal to generate a 44 MHz output clock signal having a 50% duty cycle. In another aspect, the clock divider circuit divides a 669 MHz input clock signal to generate a 45 MHz output clock signal.
A low power, low area shift register permits control over delay by dividing the shift register cells into a plurality of segments that are serially connected. A first selector provides data from a shift register input selectively to an input of one of the segments. A second selector provides data from an input or output of a selected cell of one segment of shift register cells to a shift register output.
