A shift register that is suitable for reducing the required number of clock signals as well as simplifying the configuration of an external control circuit uses a plurality of stages connected, in series, to a start pulse input line. In each stage, an output circuit responds to a first control signal to apply any one of first and second clock signals to a row line of a liquid crystal cell array and thus to charge the low line of the liquid crystal cell array, and responds to a second control signal to discharge a voltage at the row line. An output circuit responds to a clock signal different from any one of the start pulse and an output signal of the previous stage to generate the first control signal, and responds to a clock signal different from the first control signal to generate the second control signal.

A shift register for driving a pixel row in a liquid crystal display device. In the shift register, a plurality of stages are connected to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator, connected to row lines, and connected, in cascade, with respect to a scanning signal, for charging and discharging the row lines. In each stage of the shift register, an output circuit is provided with a pull-up transistor having a first input electrode for receiving a first clock signal having a delayed phase in comparison to the scanning signal, a first output electrode connected to the raw line and a first control electrode, and a pull-down transistor having a second input electrode connected to the low level voltage source, a second output electrode connected to the row line and a second control electrode. An input circuit responds to the scanning signal to generate a first control signal to be applied to the first control electrode, and responds to a second clock signal having a delayed phase in comparison to the first clock signal to generate a second control signal to be applied to the second control electrode.

A shift registers circuit having a series of cascading shift registers comprises a first transistor coupling to an output signal of a pre-stage shift register, a second transistor coupling to the first transistor, an output and a first clock signal, and a pull-down module coupling to the output, output signals of pre-stage and post-stage shift register, a second and a third voltage level. When the second transistor turns on and the first clock signal is at high voltage level, the output is at a first voltage level. When the signal of post-stage shift register is at first voltage level, the output is at the third voltage level.

A process for compensating a circuit including at least one first conductor with a specified potential, at least one second conductor generating disturbances on the first conductor by capacitive coupling, and a first bus with a reference voltage, coupled capacitively to the first conductor. The process includes the following steps: measuring of the current flowing on the first bus upon the application of a voltage to the second conductor; integrating a measured current to obtain a compensation voltage to be applied to the first conductor; and applying the compensation voltage to at least one of the rows via the compensation conductor bus, the compensation bus coupled capacitively to the rows.