Independent and cooperative multichannel memory architecture for use with master device

Claims

What is claimed is:

1. A multichannel memory architecture comprising:

at least two independent memory clusters, each of said clusters having a plurality of individually addressable data storage locations with each of said data storage locations having distinct column and row addresses; and

at least two multi-line channels, each channel including bus lines, each channel respectively coupling at least one of at least two logic units to at least one of said clusters, each logic unit being capable of controlling a memory transaction, each channel being adapted to carry address and control information and data information for conducting said memory transaction between said at least one of said logic units and said at least one of said clusters, said at least two multi-line channels providing a plurality of distinct operating modes for said memory transaction, and at least one of said multi-line channels being adapted to carry at least part of said address and control information and at least part of said data information over at least one common bus line.

2. The multichannel memory architecture of claim 1, wherein each of said plurality of clusters further comprise at least one independently addressable memory bank.

3. The multichannel memory architecture of claim 1, further comprising a plurality of master devices coupled to said multi-line channels for conducting selected data read and/or write transactions within said at least one of said clusters.

4. The multichannel memory architecture of claim 1, further comprising at least one multiplexer coupled to at least two of said at least two multi-line channels between said master device and at least one of said clusters.

5. The multichannel memory architecture of claim 1, further comprising clock input and output ports associated with each of said multi-line channels.

6. The multichannel memory architecture of claim 1, wherein a first one of said at least two logic units is coupled to at least one of said multi-line channels and to a second one of said at least two logic units.

7. The multichannel memory architecture of claim 1, wherein one of said multi-line channels provides a dedicated coupling into one of said independent memory clusters.

8. The multichannel memory architecture of claim 1, wherein each transaction has a clock signal propagating with it.

9. The multichannel memory architecture of claim 1, wherein at least one of the memory clusters comprises a refresh counter for background refresh operations of the memory cluster.

10. A multichannel memory architecture comprising:

a memory device having a plurality of independent clusters, each of said clusters having at least one independently addressable memory bank containing a plurality of individually addressable data storage locations with each of said data storage locations having distinct column and row addresses; and

a plurality of multi-line channels, each channel including bus lines, each channel respectively coupling at least one of at least two logic units to at least two of said clusters, each logic unit being capable of controlling a memory transaction, each channel being adapted to carry address and control information and data information for conducting said memory transaction between said at least one of said logic units and said at least two of said clusters, said plurality of multi-line channels providing a plurality of distinct operating modes for said memory transactions, and at least one of said multi-line channels being adapted to carry at least part of said address and control information and at least part of said data information over at least one common bus line.

11. The multichannel memory architecture of claim 10, wherein said memory device further comprises at least eight of said clusters.

12. The multichannel memory architecture of claim 10, wherein said plurality of multi-line channels further comprises at least four multi-line channels.

13. The multichannel memory architecture of claim 10, wherein particular ones of said plurality of independent memory clusters comprise a plurality of banks.

14. The multichannel memory architecture of claim 10, wherein said master device further comprises a plurality of bi-directional communication ports with each one of said ports coupled to respective ones of said plurality of multi-line channels.

15. The multichannel memory architecture of claim 10, wherein said memory device further comprises a plurality of bi-directional communication ports with each one of said ports coupled to respective ones of said plurality of multi-line channels.

16. The multichannel memory architecture of claim 15, wherein said memory device further comprises at least one multiplexer coupled to at least two of said communication ports and a portion of said plurality of clusters.

17. The multichannel memory architecture of claim 10, wherein each said cluster further comprises means for controlling addressing of associated memory banks within said cluster responsive to said address information provided on one of said multi-line channels.

18. The multichannel memory architecture of claim 10, further comprising means for synchronizing said carrying of data and address information on each of said multi-line channels.

19. The multichannel memory architecture of claim 18, further comprising means for providing a clock signal, and wherein said synchronizing means further comprises a clock signal delay unit that provides a delay to said clock signal so that said clock signal follows behind said data and address information on each of said multi-line channels.

20. The multichannel memory architecture of claim 19, wherein said synchronizing means comprises a data buffer coupled to the master device for converting a voltage level of the data and of the address information and a clock buffer coupled to the clock signal delay unit for converting a voltage level of the clock.

21. The multichannel memory architecture of claim 20, wherein the data buffer and the clock buffer are substantially identical.

22. The multichannel memory architecture of claim 10, wherein one of said multi-line channels provides a dedicated coupling into one of said banks.

23. The multichannel memory architecture of claim 10, wherein at least one of said memory clusters comprises a next-up register for permitting a new transaction to begin before a current transaction is complete.

24. A multichannel memory architecture comprising:

a memory device having a plurality of independently addressable memory banks each having a plurality of individually addressable data storage locations with each of said data storage locations having distinct column and row addresses;

a plurality of multi-line channels, each channel including bus lines, each channel respectively coupling at least one of at least two logic units to at least two of said memory banks, each logic unit being capable of controlling a memory transaction, each channel being adapted to transfer data, address and control information between said at least one of said logic units and said at least two of said memory banks; and

means for synchronizing said transfers of data, address and control information on each of said multi-line channels, at least one of said multi-line channels being adapted to carry at least part of said address and control information and at least part of said data information over at least one common bus line;

wherein said plurality of multi-line channels provide a plurality of distinct operating modes for said memory transaction.

25. The multichannel memory architecture of claim 24, further comprising means for providing a clock signal, said synchronizing means further providing a time delay to said clock signal so that said clock signal lags behind said data, address and control information on each of said multi-line channels.

26. A multichannel memory architecture comprising:

a memory device having a plurality of independently addressable memory banks each having a plurality of individually addressable data storage locations with each of said data