A universal memory bus coupled between a system's CPU and the system memory is composed of four channels; a primary channel, an identification channel, a programming channel and an expansion channel. The primary channel communicates operating system data necessary to boot the system. The identification channel communicates signals describing the device composition of the system memory. The programming channel communicates programming signals to all of the programmable memory devices within the system memory and thus allows complete programmability of those devices. The expansion channel provides data and programming access to a memory device subsequently added to the system memory.
STATEMENT OF RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Application No. 60/039,744 filed Mar. 3, 1997, the disclosure of which is herein incorporated by reference.
Included in the system are a memory module, a controller, and a voltage regulator. The memory module stores data indicating a level of voltage needed for operation. The controller obtains the data from the memory module and outputs a signal, based on the data, indicating the level of voltage needed by the memory module. The voltage regulator receives the signal from the controller, and supplies the level of voltage to the memory module in accordance with the signal.
The present invention relates to a device connection state recognizing method capable of recognizing a connection state of devices without addition of signal lines dedicated to detection. Thus, in the method according to this invention, a portion of or all of a plurality of data signal lines are connected through pull-up resistors to a high electric potential or connected through pull-down resistors to a low electric potential in accordance with the connection state of the devices, and a processing unit reads, as structure information data, a high electric potential state/low electric potential state generated by the pull-up resistor/pull-down resistor in the portion of or all the plurality of data signal lines to recognize the connection state of the devices on the basis of the read structure information data. This invention is applicable to a various types of processing units which are to be connected through a common data bus to a plurality of devices.
A memory card in accordance with the present invention allows a variety of memory devices to interface with a processor. The memory card comprises a data base which contains information about the variety of memory devices that are on the card and dual signal pairs that can be used to form different signal sets that are required to test or program the variety of memory devices. The memory card further comprises a plurality of reserved lines that can be used to form additional signal sets and a plurality memory areas. A memory card in accordance with the present invention comprises four different signal groups which allows memory modules that individually contain multiple memory types to be interfaced to a standard CPU. Such a memory bus is referred to as an X-Bus and the memory modules are referred to as X-Cards. The four signal groups of the X-Bus/X-Card combination are described below. 1. The X-Bus has a plurality of signals that connect to a device on the X-Card that contains information on all devices that exist on the X-Card. This device is referred to as the XDD (the X-Card Database Device). 2. The X-Bus also contains dual signal pairs that can be used to form different signal sets. These signal sets are required to test and or program typical memory devices such as FLASH programmable devices. 3. The X-Bus also provides a multiplicity of defined signals required to normally access most common memory types. One of these defined signals is a chip select signal (preferably #CS0), which is normally used to boot a computer system from reset. 4. Further, the X-Bus provides a multiplicity of reserved lines that can be used to form the different signal sets required for the testing, programming, and/or normal use modes of standard memory devices.
A memory module architecture that supports Flash and static memory devices in addition to dynamic memory devices. The module architecture of the present invention preferably redefines standard application of chip select signals on existing module architectures to provide requisite signaling to support Flash and static RAM devices. Use of serial presence detect signaling features of standard memory modules is also modified to provide desired identity and parameters of such an enhanced module. Extending the range of supported memory devices in an otherwise standard memory module reduces the need for special designs to accommodate different and evolving types of memory and is therefore particularly applicable to embedded systems where a variety of memory types are often utilized. A further aspect of the present invention provides for a support structure to immobilize the loose edge of the memory module opposite the electrical edge connector of the module to further enhance the module's resistance to vibration and mechanical shock by immobilizing the module with respect to rotation about the key in the socket connector.
A memory system comprising an expansion buffer and a memory expansion channel for connecting a large array of memory devices, such as Direct RDRAMs, to a memory controller. The memory devices are partitioned into subsets of memory devices so that each subset is connected to a unique memory channel for sending and receiving data. The expansion buffer and memory expansion channel provide communication with the memory devices via control packets on the expansion bus, where each control packet has a channel identification field to store a channel identifier; and via request packets on the expansion bus, where each request packet is associated with a control packet. The expansion buffer routes a request packet to a unique channel based upon the channel identifier stored in the associated control packet.
