A successive approximation analog/digital ("A/D") converter that converts an analog input voltage to a digital value for output in a manner enabling a reduction in power consumption. The A/D converter includes a comparator that outputs a referencing result signal by comparing an analog input voltage against a reference voltage. A D/A converter outputs the reference voltage to a comparator in correspondence to a digital voltage signal. A successive approximation register outputs the digital voltage signal to the D/A converter in correspondence to a conversion control signal. A conversion control device outputs the conversion control signal to the successive approximation register in correspondence to the referencing result signal to continue operation of the AND converter until the difference between the analog input voltage and the reference voltage converges to within a specific tolerance range. An output unit holds the digital voltage signal from the successive conversion register at a point in time at which the difference has converged to within the tolerance range and outputs the digital voltage signal as a digital output signal. An operating mode selection circuit judges an effective/non-effective state of the analog input voltage, enables an A/D conversion operation by entering a conversion mode when the analog input voltage is judged to be effective, and disables the A/D conversion operation by entering a standby mode when the analog input voltage is judged to be non-effective.
A successive approximation A/D converter which converts an analog signal to a digital signal by carrying out successive A/D conversions of the analog signal. It carries out, for a least significant bit of the digital signal, A/D conversion of the analog signal using a reference voltage corresponding to a previous digital signal obtained as a result of a previous A/D conversion, increments a current digital signal, which is obtained as a result of the latest A/D conversion, when the least significant bit of the current digital signal is "1", and decrements the current digital signal when the least significant bit is "0". This makes it possible to solve a problem of a conventional successive approximation A/D converter in that the tracking ability of the digital signal to variations of the analog signal is degraded because of the long update period involved in the increasing number of the bits of the A/D converter, if full bit conversion is carried out.
An input circuit of a one-chip microcomputer is connected to an external switching circuit. When an analog input signal of a significant level generated in the external switching circuit is received at an analog input terminal of the input circuit, an A/D conversion start request signal is generated in an A/D conversion start request generating circuit and is sent to an A/D converter. The operation of the A/D converter is started in response to the A/D conversion start request signal, the analog input signal received at the analog input terminal is converted into digital data, and an A/D conversion finish signal is sent from the A/D converter to a CPU of the one-chip microcomputer. The operation of the CPU is started in response to the A/D conversion finish signal, and the digital data is readout to the CPU. Therefore, the A/D converter, the CPU or a clock is not operated to wait for an analog input signal generated in the external switching circuit, but the A/D converter is operated for the A/D conversion, and the CPU is operated to read out the digital data. Accordingly, an electric power consumed in the A/D converter, the CPU and the clock can be reduced.
A codec having an analog-to-digital converter and is made in the form of a discrete electronic component. The codec has an analog-to-digital conversion circuit (14) for converting an analog input signal into a sequence of digital samples. An output stage (16) is provided for supplying said sequence in serial form outside said component (2). A first signal detection circuit (22, 24, 26, 28)is provided for indicating outside said component the presence or absence of significant data in said sequence.
A programmable input voltage range analog-to-digital converter in which a split gate oxide process allows the use of high voltage (.+-.15 volt) switches on the same silicon substrate as standard sub-micron 5 volt CMOS devices. With this process, the analog input voltage can be sampled directly onto one or more sampling capacitors without the need for prior attenuation circuits. By only sampling on a given ratio of the sampling capacitors, the analog input can be scaled or attenuated to suit the dynamic range of a subsequent ADC. In the system of the present invention, the sampling capacitor can be the actual capacitive redistribution digital-to-analog converter (CapDAC) used in a SAR ADC itself, or a separate capacitor array. By selecting which bits of the CapDAC or separate sampling array to sample on, one can program the input range. Once the analog input signal has been attenuated to match the allowed dynamic range of the SAR converter, traditional SAR techniques can be used to convert the input signal to a digital word. Other conversion technologies, such as sigma-delta and pipeline, can also be used in conjunction with the inventive system.
A successive-approximation analog-digital converter including a logic control circuit timed by means of an external clock signal clock. The logic control circuit includes a register containing a first digital signal formed of N bits, which is the product of a first analog-digital conversion. The logic control circuit is suitable for producing a second digital signal formed of N bits through a second analog-digital conversion in N clock cycles. This analog-digital converter converts the second digital signal sent by the logic circuit to a second analog signal. A comparator compares the first analog signal with the second analog signal which has been input to the analog-digital converter. The converter includes a device which enables the increase of the first analog signal in output from the digital-analog converter and in input to the comparator by a preset value (Voffs) when the bit of the first digital signal which corresponds in position to the bit of the second digital signal which must be decided in a clock cycle is zero.
