A sigma-delta modulator (10) and a method for digitizing an analog signal. The sigma-delta modulator includes at least one switch (16) for altering the order of the sigma-delta modulator (10). The order of the sigma-delta modulator (10) is changed based on the communication protocol of the received analog signal. More particularly, the order of the sigma-delta modulator (10) is increased for communication protocols having wide information-bandwidths. Alternatively, the order of the sigma-delta modulator (10) is decreased for communication protocols having narrow information-bandwidths.
The present invention discloses an automatic gain control (AGC) feedback-referenced sigma-delta modulating device provided for processing an analog signal received therein. This device includes an automatic gain controller (AGC) for receiving processing the analog input signal for generating an AGC feedback including a set of positive and negative AGC reference voltages. This device further include a sigma-delta modulator for receiving the analog input signal and the AGC feedback of the set of the positive and negative AGC reference voltages for generating a one binary bit output therefrom. In a preferred embodiment, the automatic gain controller (AGC) includes a peak detector for receiving and detecting a peak input voltage of the analog input signal. The automatic gain controller (AGC) further includes a maximum gain control block for receiving the peak input voltage from the peak value detector for generating a maximum gain controlled peak value Vp. And, the automatic gain controller (AGC) further includes a positive-and-negative AGC reference voltage (Vref.sup.+_ AGC, Vref.sup.-_ AGC) generation block for receiving and applying the maximum gain controlled peak value Vp to generate a positive AGC reference voltage Vref.sup.+_ AGC and a negative AGC reference voltage Vref-_AGC.
The output of a first integrator is quantized in a quantizer. The quantized signal is subjected to D/A conversion, successively output to a plurality of output paths by a first switching circuit, sampled and held by a plurality of charge-holding circuits of a first feedback circuit, and successively output by a second switching circuit to one of the input terminals of a subtractor. On the other hand, the output signal of the first integrator is successively output by a third switching circuit to a plurality of output paths, sampled and held by a plurality of charge-holding circuits of a second feedback circuit, and successively input to the other input terminal of the subtractor by a fourth switching circuit along with signals held in an input portion, which samples and holds input analog signals. By doing so, a plurality of signals with different sampling timings are integrated accumulatively by the subtractor and the first integrator. When integration functions used to obtain an n-th order noise-shaping effect are multiplexed and operated using a single integrator, the integrator's current consumption can be suppressed.
In a delta-sigma modulator including first and second subtractors, first and second integrators, a quantizer, and a DA converter, a first feedback circuit includes first charge holding circuits which hold charges of the analog signal from the DA converter for different sampling intervals, can change a feedback amount of the analog signal from the DA converter, and outputs the analog signal from each first charge holding circuits to the second subtractor. A second feedback circuit includes second charge holding circuits which hold charges of the analog signal from the second integrator for different sampling intervals, can change a feedback amount of the analog signal from the second integrator, and outputs an analog signal from each of the second charge holding circuits to the second subtractor. A controller switches an order of filter characteristic of the delta sigma modulator by changing feedback amounts of the first and second feedback circuits.
Sigma-delta analog-to-digital converter topology with an error signal branch including a subtractor (10), a loop filter (4), and a quantizer (6), and a feedback branch including a digital-to-analog converter (8). The gain error caused by a return-to-zero switch in the feedback branch is cancelled by moving the return-to-zero switch (20) to the signal error branch.