Fault tolerant subrate switching - Patent Review 6088329

What is claimed is:

1. A method of operating each of a plurality of processing modules in an apparatus for processing a plurality of input signals, wherein the apparatus comprises redundant processing planes, wherein each processing plane is for processing the plurality of input signals, and each processing plane includes at least two of the processing modules, each processing module being connected to receive a subset of the input signals directly from an input signal source coupled to the apparatus and each processing module being further connected to receive a remaining subset of the input signals from remaining processing modules on the same processing plane; and wherein each processing module generates an output signal comprising components derived from the plurality of input signals, the method comprising the steps of:

detecting whether any of the remaining processing modules on the same processing plane are faulty; and

in response to detection of a faulty processing module in the same processing plane, substituting a signal representing a logical zero for those components of the output signal that are derived from the faulty processing module.

2. The method of claim 1, wherein each processing module is a switching module.

3. The method of claim 1, wherein each processing module is a subrate switching module.

4. The method of claim 3, wherein subrate switching is performed on a bit-by-bit basis.

5. The method of claim 1, wherein each processing module is a normal rate switching module that switches data units comprising more than one bit.

6. The method of claim 1, further comprising the step of generating a signal indicating that at least one component of the output signal is derived from one or more faulty processing modules.

7. A method of processing a plurality of input signals in an apparatus comprising redundant processing planes and means for receiving an output signal from each of the redundant processing planes, wherein each processing plane is for processing the plurality of input signals, and each processing plane includes at least two processing modules, each processing module being connected to receive a subset of the input signals directly from an input signal source coupled to the apparatus and each processing module being further connected to receive a remaining subset of the input signals from remaining processing modules on the same processing plane; and wherein each processing module generates an output signal comprising components derived from the plurality of input signals, the method comprising the steps of:

in each processing module, detecting whether any of the remaining processing modules on the same processing plane are faulty;

in response to detection of a faulty processing module in the same processing plane, substituting a signal representing a logical zero for those components of the output signal that are derived from the faulty processing module; and

in the means for receiving the output signal from each of the redundant processing planes, logically OR'ing the received output signals together.

8. The method of claim 7, further comprising the step of:

in the means for receiving the output signal from each of the redundant processing planes, detecting that each of the output signals received from corresponding processing modules in the redundant processing planes is invalid; and

wherein the step of logically OR'ing the received output signals together is performed in response to detecting that each of the received output signals is invalid.

9. The method of claim 7, wherein each processing module is a switching module.

10. The method of claim 7, wherein each processing module is a subrate switching module.

11. The method of claim 10, wherein subrate switching is performed on a bit-by-bit basis.

12. The method of claim 7, wherein each processing module is a normal rate switching module that switches data units comprising more than one bit.

13. The method of claim 7, further comprising the steps of:

in the means for receiving the output signal from each of the redundant processing planes, detecting that one of two redundant processing modules is faulty, and in response to said detection, selecting for further processing only the output signal from a non-faulty one of the two redundant processing modules.

14. The method of claim 7, further comprising the step of, in each processing module, generating a signal indicating that at least one component of the output signal is derived from one or more faulty processing modules.

15. A method of operating each of a plurality of processing modules in an apparatus for processing a plurality of input signals, wherein the apparatus comprises redundant processing planes, wherein each processing plane is for processing the plurality of input signals, and each processing plane includes at least two of the processing modules, each processing module being connected to receive a subset of the input signals directly from an input signal source coupled to the apparatus and each processing module being further connected to receive a remaining subset of the input signals from remaining processing modules on the same processing plane; and wherein each processing module generates an output signal comprising components derived from the plurality of input signals, the method comprising the steps of:

detecting whether any of the remaining processing modules on the same processing plane are faulty; and

in response to detection of a faulty processing module in the same processing plane, substituting a signal representing a logical one for those components of the output signal that are derived from the faulty processing module.

16. The method of claim 15, wherein each processing module is a switching module.

17. The method of claim 15, wherein each processing module is a subrate switching module.

18. The method of claim 17, wherein subrate switching is performed on a bit-by-bit basis.

19. The method of claim 15, wherein each processing module is a normal rate switching module that switches data units comprising more than one bit.

20. The method of claim 15, further comprising the step of generating a signal indicating that at least one component of the output signal is derived from one or more faulty processing modules.

21. A method of processing a plurality of input signals in an apparatus comprising redundant processing planes and means for receiving an output signal from each of the redundant processing planes, wherein each processing plane is for processing the plurality of input signals, and each processing plane includes at least two processing modules, each processing module being connected to receive a subset of the input signals directly from an input signal source coupled to the apparatus and each processing module being further connected to receive a remaining subset of the input signals from remaining processing modules on the same processing plane; and wherein each processing module generates an output signal comprising components derived from the plurality of input signals, the method comprising the steps of:

in each processing module, detecting whether any of the remaining processing modules on the same processing plane are faulty;

in response to detection of a faulty processing module in the same processing plane, substituting a signal representing a logical one for those components of the output signal that are derived from the faulty processing module; and

in the means for receiving the output signal from each of the redundant processing planes, logically AND'ing the received output signals together.

22. The method of claim 21, further comprising the step of:

in the means for receiving the output signal from each of the redundant processing planes, detecting that each of the output signals received from corresponding processing modules in the redundant processing planes is invalid; and

wherein the step of logically AND'ing the received output signals together is performed in response to detecting that each of the received output signals is invalid.

23. The method of claim 21, wherein each processing module is a switching module.

24. The method of claim 21, wherein each processing module is a subrate switching module.

25. The method of claim 24, wherein subrate switching is performed on a bit-by-bit basis.

26. The method of claim 21, wherein each processing module is a normal rate switching module that switches data units comprising more than one bit.

27. The method of claim 21, further comprising the steps of:

in the means for receiving the output signal from each of the redundant processing planes, detecting that one of two redundant processing modules is faulty, and in response to said detection, selecting for further processing only the output signal from a non-faulty one of the two redundant processing modules.

28. The method of claim 21, further comprising the step of, in each processing module, generating a signal indicating that at least one component of the output signal is derived from one or more faulty processing modules.

29. A processing module for use with a plurality of like processing modules in an apparatus for processing a plurality of input signals, wherein the apparatus comprises redundant processing planes, wherein each processing plane is for processing the plurality of input signals, and each processing plane includes at least two of the processing modules, the processing module comprising:

means for receiving a subset of the input signals directly from an input signal source coupled to the apparatus;

means for receiving a remaining subset of the input signals from remaining processing modules on the same processing plane;

means for generating an output signal comprising components derived from the plurality of input signals;

means for detecting whether any of the remaining processing modules on the same processing plane are faulty; and

means, responsive to a detection that at least one of the remaining processing modules on the same processing plane is faulty, for substituting a signal representing a logical zero for those components of the output signal that are derived from the faulty processing module.

30. The processing module of claim 29, wherein each processing module is a switching module.

31. The processing module of claim 29, wherein each processing module is a subrate switching module.

32. The processing module of claim 31, wherein each subrate switching module performs switching on a bit-by-bit basis.

33. The processing module of claim 29, wherein each processing module is a normal rate switching module that switches data units comprising more than one bit.

34. The processing module of claim 29, further comprising means for generating a signal indicating that at least one component of the output signal is derived from one or more faulty processing modules.

35. An apparatus for processing a plurality of input signals, comprising:

redundant processing planes, wherein each processing plane is for processing the plurality of input signals, and each processing plane includes at least two processing modules, each processing module including:

means for receiving a subset of the input signals directly from an input signal source coupled to the apparatus;

means for receiving a remaining subset of the input signals from remaining processing modules on the same processing plane;

means for generating an output signal comprising components derived from the plurality of input signals;

means for detecting whether any of the remaining processing modules on the same processing plane are faulty; and

means, responsive to detection of a faulty processing module in the same processing plane, for substituting a signal representing a logical zero for those components of the output signal that are derived from the faulty processing module; and

means for receiving an output signal from each of the redundant processing planes, including:

means for logically OR'ing the received output signals together.

36. The apparatus of claim 35, wherein the means for receiving the output signal from each of the redundant processing planes further comprises means for detecting that each of the output signals received from corresponding processing modules in the redundant processing planes is invalid; and

wherein the means for logically OR'ing the received output signals together operates in response to a detection that each of the received output signals is invalid.

37. The apparatus of claim 35, wherein each processing module is a switching module.

38. The apparatus of claim 35, wherein each processing module is a subrate switching module.

39. The apparatus of claim 38, wherein each subrate switching module performs subrate switching on a bit-by-bit basis.

40. The apparatus of claim 35, wherein each processing module is a normal rate switching module that switches data units comprising more than one bit.

41. The apparatus of claim 35, further comprising:

in the means for receiving the output signal from each of the redundant processing planes, means for detecting that one of two redundant processing modules is faulty; and

means, responsive to a detection that one of two redundant processing modules is faulty, for selecting for further processing only the output signal from a non-faulty one of the two redundant processing modules.

42. The apparatus of claim 35, further comprising, in each processing module, means for generating a signal indicating that at least one component of the output signal is derived from one or more faulty processing modules.

43. A processing module for use with a plurality of like processing modules in an apparatus for processing a plurality of input signals, wherein the apparatus comprises redundant processing planes, wherein each processing plane is for processing the plurality of input signals, and each processing plane includes at least two of the processing modules, the processing module comprising:

means for receiving a subset of the input signals directly from an input signal source coupled to the apparatus;

means for receiving a remaining subset of the input signals from remaining processing modules on the same processing plane;

means for generating an output signal comprising components derived from the plurality of input signals;

means for detecting whether any of the remaining processing modules on the same processing plane are faulty; and

means, responsive to a detection that at least one of the remaining processing modules on the same processing plane is faulty, for substituting a signal representing a logical one for those components of the output signal that are derived from the faulty processing module.

44. The processing module of claim 43, wherein each processing module is a switching module.

45. The processing module of claim 43, wherein each processing module is a subrate switching module.

46. The processing module of claim 45, wherein each subrate switching module performs switching on a bit-by-bit basis.

47. The processing module of claim 43, wherein each processing module is a normal rate switching module that switches data units comprising more than one bit.

48. The processing module of claim 43, further comprising means for generating a signal indicating that at least one component of the output signal is derived from one or more faulty processing modules.

49. An apparatus for processing a plurality of input signals, comprising:

redundant processing planes, wherein each processing plane is for processing the plurality of input signals, and each processing plane includes at least two processing modules, each processing module including:

means for receiving a subset of the input signals directly from an input signal source coupled to the apparatus;

means for receiving a remaining subset of the input signals from remaining processing modules on the same processing plane;

means for generating an output signal comprising components derived from the plurality of input signals;

means for detecting whether any of the remaining processing modules on the same processing plane are faulty; and

means, responsive to detection of a faulty processing module in the same processing plane, for substituting a signal representing a logical one for those components of the output signal that are derived from the faulty processing module; and

means for receiving an output signal from each of the redundant processing planes, including:

means for logically AND'ing the received output signals together.

50. The apparatus of claim 49, wherein the means for receiving an output signal from each of the redundant processing planes further includes means for detecting that each of the output signals received from corresponding processing modules in the redundant processing planes is invalid; and

wherein the means for logically AND'ing the received output signals together operates in response to a detection that each of the received output signals is invalid.

51. The apparatus of claim 49, wherein each processing module is a switching module.

52. The apparatus of claim 49, wherein each processing module is a subrate switching module.

53. The apparatus of claim 52, wherein each subrate switching module performs subrate switching on a bit-by-bit basis.

54. The apparatus of claim 49, wherein each processing module is a normal rate switching module that switches data units comprising more than one bit.

55. The apparatus of claim 49, further comprising:

in the means for receiving the output signal from each of the redundant processing planes, means for detecting that one of two redundant processing modules is faulty; and

means, responsive to a detection that one of two redundant processing modules is faulty, for selecting for further processing only the output signal from a non-faulty one of the two redundant processing modules.

56. The apparatus of claim 49, further comprising, in each processing module, means for generating a signal indicating that at least one component of the output signal is derived from one or more faulty processing modules.

Description Submit all comments and votes

BACKGROUND

The present invention relates to subrate switching, and more particularly to techniques for achieving fault tolerance in subrate switches.

Because of the ever-increasing demand for telecommunications services, it is vital that a telecommunications system use its resources in an efficient manner. Inefficiencies can result, for example, by allocating a resource to one user who cannot utilize the full capacity of that resource. One well-known approach to alleviating this type of problem is to utilize Time Division Multiple Access (TDMA) techniques. Such techniques permit a plurality of users to share a single transmission medium. Essentially, the medium is divided up into a series of time slots, each of which can potentially be assigned to a different user. Thus, a first user might transmit information via the transmission medium during a first time slot, a second user might transmit information during a second time slot, and so on. In order to implement such a system, a so-called "normal rate switch" may be used. In telecommunication systems such as the Global System for Mobile communication (GSM), normal rate switching works at a transfer rate of 64 Kbit/s. The normal rate switch has a plurality of inputs, each coupled to receive information from a respective one of the users. The normal rate switch also has a plurality of outputs, each one corresponding to a particular time slot in the TDMA frame. The normal rate switch is capable of switching the information from any one of its inputs to any of its outputs (time slots). In this way, a TDMA frame may be composed from the data supplied by the various users. TDMA techniques are well known, and a complete discussion of them would go well beyond the scope of this disclosure.

Another way in which telecommunication system designers have been able to make more efficient use of system capacity is by decreasing the number of bits that it takes to encode the same piece of information. For example, in digital mobile telephony, speech information is coded by a speech coder in such a way that a lower transfer rate over the radio connection is obtained. In GSM, for example, so-called "full rate" speech coding is capable of achieving a transfer rate of less than 16 kbit/s. This is one fourth of the normal Pulse Code Modulation (PCM) transmission rate that is employed by GSM. In this case, one channel occupies only two bits in an 8-bit PCM word. In order to prevent the remaining bits from being unused, it has therefore been suggested that four such coded channels be packed into a PCM word that is sent to the public telephone network. This packing can, for instance, be done in a base station controller (BSC).

The packing of such coded channels into a PCM word is efficient only so long as each bit of the coded information is conveying information. However, this may not always be the case. For example, so-called "half rate" channels have been defined that have a transfer rate of less than 8 kbit/s. Such channels require only one of the eight bits in a PCM word. In this case, it is desirable to pack several "half rate" channels in one and the same PCM word. Traditional telecommunications systems perform switching at a normal rate. However, when full or half rate information is supplied at an input of the normal rate switch, it leaves a number of input bits unused. This means that some of the bits appearing at the output of the normal rate switch will not convey any information, thereby constituting a waste of system resources.

In view of the above, so-called "subrate" switching has been proposed in which traffic is circuit switched on a bit level instead of a byte level. In order to permit the intermixing of, for example, full rate and half rate channels, subrate switching is usually performed by connecting the output of a normal switch to the input of a subrate switch, with a feedback connection from the subrate switch back to an input of the normal switch. Such an arrangement is depicted in FIG. 1, and described, for example, in U.S. Pat. No. 5,453,985, which issued to Ghisler on Sep. 26, 1995, and which is hereby incorporated herein by reference.

In FIG. 1, traffic is depicted flowing in one direction (from the left to the right). Of course, those skilled in the art will appreciate that traffic typically flows in both directions. A first group of traffic interface ports (#1 to n) of the normal rate switch 14 is allocated for traditional normal rate traffic. A second set of traffic interface ports of the normal rate switch 14, (#n+1) through (#n+m), is allocated for routing subrate traffic between the normal rate switch 14 and the subrate switch 12. The subrate switch 12 includes a plurality of incoming and outgoing interface ports (#1 to m). Accordingly, the subrate switch 12 is only connected to the normal rate switch and does not interface with external telecommunications equipment. This further enhances its modularity and minimizes its impact on existing equipment.

Although this is not depicted in FIG. 1, normal rate channels may be switched through the normal rate switch 14 from, for example, an in-MUP A (where "MUP" denotes "Multiple Position node") carried by the frame terminated at port #1 to, for example, an out-MUP B carried by the frame terminated at port #n. The illustrated frames can be either Synchronous Digital Hierarchy (SDH)-, SONET, or Plesiochronous Digital Hierarchy (PDH)-type frames.

The depicted example shows connection of a subrate channel C to a subrate channel D at a rate corresponding to one-eighth of the normal rate. In other words, subrate channel C corresponds to one bit at bit location 6 in the time slot that is switched ultimately to bit position 2 in the time slot out-MUP B. Thus, the normal rate time slot that contains subrate channel C received at in-MUP A (at port #1) is routed through normal rate switch 14 to out-MPU X (at port #n+1). Note that subchannel C remains at bit location 6. The time slot including subchannel C is then routed to port #1 of subrate switch 12 which performs the subrate switching, that is, switching subchannel C at bit location 6 in the incoming time slot to subchannel D at bit position 2 in a different outgoing time slot. The outgoing time slot including subchannel D is routed from subrate switch port #m to incoming MUP Y (at port #n+m) of the normal rate switch 14 and is then routed through the normal rate switch to outgoing MUP B (at port #n).

Referring now to FIG. 2, subrate switch module units of the type described above will now be described as a modular add-on switch to an existing telecommunications switch, namely, the group switch subsystem (GSS) of the well known Ericsson AXE-10 telecommunications switching system. The group switch subsystem 30 employs a time-space-time (TST) switch architecture. Incoming and outgoing calls are interfaced to the group switch subsystem through switching network terminals (SNTs). Input switching network terminals 32 are connected to an incoming time switch module (TSM) 34. The time switch modules 34 are connected to a space switching module (SPM) 36. The subrate switch 38 is also interfaced with the space switching module 36 via time switch modules 34'. A clock module 40 synchronizes the timing of all modules in the group switch subsystem 30. A central processor (not shown) and regional processors 40, maintain a database map of system configurations for the different types of equipment connected to the switch and the different types of channels at switch interfaces. Using this database information, the processors control the operation and routing of switching paths through the group switch subsystem 30.

More particularly, the subrate switch 38 is connected to the normal rate group switch by eight (0-7) TSMs 34'. Each TSM 34' interface includes 512 time slots. As described above, each bit of each outgoing time slot in the subrate switch module corresponds to one location in a subrate switch module control store. Thus, the contents of each control store location defines a specific bit in a switch store (SS) to be read. In order to connect a channel of more than 8 kbps, the regional processors 40 must write addresses in more than one control store location. For example, to set up a 24 kbps connection (3 bits of a normal rate 8-bit time slot), requires that three addresses must be written in control stores (i.e., one control store location per bit).

The actual detailed architecture and operation of the group switch subsystem is known and not repeated here. In brief, the time switch modules (TSMs) implement time switching, and the space switch module (SPM) implements space switching. The TSMs handle the transmission and reception of speech samples using various switch stores. Speech samples are written into an incoming speech store in a fixed order, but when those samples are read out, the order is determined by addresses in a control store. The time switch modules also have an additional control store which is used to control the operation of electronic gates in the space switch module (SPM) to selectively transfer speech and data through the group switch. In essence, this space switch control store is used to connect incoming and outgoing TSMs.

FIG. 3 shows one particular implementation of a subrate switch module architecture in this group switch embodiment. In order to provide convenient implementation and maintenance of the subrate switch 38 in the group switch subsystem 30, the subrate switch 38 may be partitioned into units corresponding to the size of a time switch module (TSM). A number of partitioned subrate switch modules 45 correspond, for example, to a subrate switch 12, as depicted in FIG. 1. Each subrate switch module 45 includes an outlet going to only one time switching module (TSM). Moreover, each subrate switch module 45 includes inlets from TSMs 34' connected to the subrate switch (SRS) 38.

The procedure for setting up and releasing a two-way subrate connection on demand in this group switch subsystem (GSS) embodiment will now be described. An "on-demand" subrate connection is initiated by the generation of a subrate path signal from the GSS user. That signal contains data relating to the incoming GSS-MUP, the incoming subchannel position, the outgoing subchannel position, and the outgoing GSS-MUP. Data related to subchannel position also identify the particular rate of the subrate connection required.

Upon receiving the subrate connection command, the central/regional processors establish the three paths that constitute a subrate connection: the incoming carrier, outgoing carrier, and subrate switch path. Of course, the incoming and outgoing carriers may be established as on-demand connections or as semi-permanent connections. The release of the subrate two-way connection is ordered by the GSS-user; the release signal contains the in-MUP and the subchannel position in the in-MUP. Once received, the subrate connection in the subrate switch is released. The two carrier connections are released if no other subrate connections exist on them.

The above description addresses the components and techniques that are utilized to accomplish the switching that must be performed in an exemplary telecommunications system. However, it is typically additionally necessary to include redundancy of components in the switching system in order to achieve the desired quality of service. That is, for each component whose failure rate exceeds requirements, a redundant component is provided that operates in parallel with the first component. With this arrangement, a failed component can electronically be switched out and replaced by its still-functioning "twin", thereby maintaining a quality of service.

For example, each of the subrate switch 38, the time switch modules 34, 34', and the space switching module 36 depicted in FIG. 2 may be duplicated by one or more redundant modules operating in parallel. To accommodate this redundancy, each of the modules must be designed to accept inputs from each "plane" of redundant components, and must also be designed to distribute its output signals to a plane of redundant components. For example, consider the case in which each of the TSMs 34' has a redundant component, and that the pair of components are denoted TSMx.sub.A and TSMx.sub.B (where, in this example, the "x" may be any number from zero to seven in correspondence with one of the eight TSMs 34' depicted in FIG. 2). To accommodate this redundancy, the subrate switch 38 might be modified as shown in FIG. 4. The modified subrate switch 38' comprises a number of subrate switching modules 60, individually denoted M0 . . . M7. Each subrate switching module Mx 60 comprises a selector 51, a driver 50 and a subrate switch matrix 42. In the modified subrate switching module 38', the outputs from each subrate switch matrix 42 must be supplied to each TSM plane (i.e., to each of the units TSMx.sub.A 34' and TSMx.sub.B 34'). Additionally, each driver 50 now receives its input from the selector 51 that supplies at its output a selected one of its inputs, either TSMx.sub.A or TSMx.sub.B. For simplicity, a controller for the selector is not depicted in the figure. Those having ordinary skill in the art will recognize that any such controller would generate its control signal as a function of which of the TSMs is operating normally.

Now consider an aspect of the design related to the fact that in the switching system, each of the SRS's 38' will also be replicated. In FIG. 5, two SRS planes 38' are shown, respectively designated "A" and "B". In order to simplify the following discussion, only one TSM plane 70 is shown, although the switching system may include redundant TSM planes 70 as described previously. In order to further simplify the discussion, it will now be assumed that each SRS 38' has only four subrate switching modules 60 (designated M0, M1, M2 and M3) instead of the eight shown in FIG. 4. The TSM plane 70 will also be assumed to have four TSMs 34' internally, for receiving the respective outputs from corresponding subrate switching modules 60 inside the SRS 38'. Although, in FIG. 5, each of the internal connections 55 within each SRS 38' is depicted connecting only adjacent subrate switching modules 60, in reality it designates a connection from the input of one subrate switching module 60 to each of the other subrate switching modules 60 in the SRS 38', as fully shown in FIG. 4.

Conventionally, if a fault occurs in a subrate switching module 60, for example M1 in SRS plane A, then plane A is taken down completely and only SRS plane B is used. This is schematically depicted in FIG. 5 by means of the absence of any indicated connection between SRS plane A and TSM plane A. If plane B then experiences a fault in one of its subrate switching modules 60, such as M3, then a double fault situation has occurred, permitting SRS plane B to maintain traffic only between subrate switching modules M0 and M1, between M0 and M2, and between M1 and M2. (Traffic in SRS plane A is not considered here, because this module was previously shut down.) Thus, in SRS plane B, all traffic between M0 and M3, between M1 and M3, and between M2 and M3 is negatively affected.

In view of the above, it is desirable to provide components in a switching system that are capable of operating correctly even after a double fault, as described above, occurs.

SUMMARY

It is therefore an object of the present invention to provide an improved processing module, including an improved switching module, for use with a redundant processing module, wherein the improved processing module generates an output that facilitates recovery of valid processed data in the event of a double fault.

It is a further object of the present invention to provide a processing system, including a switching system, that is capable of recovering valid data even when redundant components are generating invalid processed data output signals.

In accordance with one aspect of the present invention, the foregoing and other objects are achieved in processing modules for use in an apparatus for processing a plurality of input signals, wherein the apparatus comprises redundant processing planes, wherein each processing plane is for processing the plurality of input signals, and each processing plane includes at least two of the processing modules, each processing module being connected to receive a subset of the input signals directly from an input signal source coupled to the apparatus and each processing module being further connected to receive a remaining subset of the input signals

from remaining processing modules on the same processing plane; and wherein each processing module generates an output signal comprising components selected from the plurality of input signals. The processing module detects whether any of the remaining processing modules on the same processing plane are faulty; and if so, it substitutes a signal representing, in one embodiment, a logical zero for those portions of the output signal that are selected to include one or more components from the faulty processing module. The output of this processing module facilitates the recovery of valid data when redundant processing modules are each generating invalid data.

In another aspect of the invention, the processing performed by each of the modules is switching.

In another aspect of the invention, the apparatus further includes hardware for receiving an output signal from each of the redundant processing planes. When the means for receiving the output signal from each of the redundant processing planes detects that each of the output signals received from corresponding processing modules in the redundant processing planes is invalid; it responds by, in one embodiment, logically OR'ing the received output signals together. In this way, the likelihood of recovering a valid output signal is increased. In one embodiment of the invention in which the processing is switching, each processing module is a subrate switching module. In alternative embodiments, the inventive concepts may be applied to other types of switching, and other types of processing as well.

In alternative embodiments, the counterpart st