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FIELD OF THE INVENTION
The present invention relates generally to video, audio, graphics, input/output and other processing functions in set top box applications. More particularly, the present invention relates to a processing system with an application specific
integrated circuit (ASIC) processor which provides video, audio, graphics and input/output processing functions and is particularly well-suited for use in set top box applications.
RELATED APPLICATIONS
The present application is related to the following U.S. patent applications, all filed concurrently herewith and assigned to the present assignee: Ser. No. 08/729,547 now U.S. Pat. No. 5,926,647 entitled "Processing System With Dynamic
Alteration of a Color Look-Up Table"; Ser. No. 08/729,545 now U.S. Pat. No. 5,953,691 entitled "Processing System With Graphics Data Prescaling"; Ser. No. 08/728,678 now U.S. Pat. No. 5,790,842 entitled "Processing System With Simultaneous
Utilization of Multiple Clock Signals"; Ser. No. 08/729,544 entitled "Processing System With Register-Based Process Sharing"; Ser. No. 08/731,343 now U.S. Pat. No. 5,889,949 entitled "Processing System With Memory Arbitration"; Ser. No. 08/731,218
now U.S. Pat. No. 5,793,427 entitled "Processing System With Delta-Based Video Data Encoding"; and Ser. No. 08/731,217 now U.S. Pat. No. 5,923,385 entitled "Processing System With Single-Buffered Display Capture."
BACKGROUND OF THE INVENTION
Multimedia distribution systems are becoming increasingly important vehicles for delivering video, audio and other data to and from remote users. Such distribution systems include cable or community access television (CATV) systems, telephone
systems and computer networks. A set top box may be used as an interface between the distribution system and a television set, computer or other type of remote user terminal. The set top box typically provides functions such as input/output processing
of video, audio and other data, audio and video demultiplexing and decompression, graphics overlay processing for use in electronic program guides and the like, entitlement controj for video on demand (VOD), near video on demand (NVOD) and pay-per-view
(PPV) applications, and remote control user interfaces.
A conventional set top box generally provides the above-noted functions using a multiplicity of dedicated stand-alone integrated circuits, each having its own separate support circuitry and protocols to provide, for example, memory access and
other processing functions. This may be attributed in part to the fact that many of the circuits used in set top box applications are general-purpose devices designed to support a broad array of applications. As a result, there is considerable overlap
in many of the circuit functions, as well as potential incompatibilities which lead to slower processing speed and other inefficiencies. The conventional set top boxes are therefore not only unduly complex and expensive, but also fail to provide optimal
levels of performance. Widespread implementation of multimedia distribution systems using cable, telephone and/or computer networks will depend in large part upon reducing the complexity and cost of set top box hardware.
As is apparent from the above, there is a need for an improved processing system suitable for use in set top box applications and which can be configured to utilize shared processing hardware to thereby provide video, audio, graphics,
input/output communication and other functions with improved efficiency and reduced cost and complexity.
SUMMARY OF THE INVENTION
The present invention involves apparatus and methods for providing video, audio, graphics, input/output communication and other processing functions in set top boxes and other applications with reduced cost and complexity. In one embodiment, the
invention is implemented as an application-specific integrated circuit (ASIC) processor suitable for use in a set top box or other processing system to improve hardware efficiency and throughput performance relative to conventional systems.
One aspect of the invention involves a method and apparatus for prescaling graphics data for use in a graphics overlay operating mode. In an exemplary embodiment, a method and apparatus are provided for processing a stream of RGB pixel data in a
graphics processor. The RGB pixel data for a given pixel are first converted to luminance and chrominance data for that pixel. The luminance and chrominance data are then prescaled by a blending value associated with the given pixel. An interpolation
operation is performed on the luminance and chrominance data as well as on the blending value for the given pixel using corresponding luminance and chrominance data and blending values for at least one other pixel in the stream. This interpolation may
include operations such as horizontal filtering and may also include chroma filtering to convert the luminance and chrominance data into a 4:2:2 chrominance format compatible with MPEG-2 video. The interpolation operation produces interpolated luminance
and chrominance data and an interpolated blending value for the given pixel. A video signal to be combined with the graphics data is then scaled using the interpolated blending value. The scaled video signal is combined with the interpolated luminance
and chrominance data for the given pixel to provide a combined video/graphics signal suitable for display.
Another aspect of the invention involves a technique for dynamic alteration of a color look-up table (CLUT) pallet identifier in response to one or more key codes placed in an input data stream. In an exemplary embodiment, a method and apparatus
are provided for converting an input data stream including a sequence of input data blocks into a converted stream suitable for addressing a look-up table. The look-up table may be a 256.times.16 table which requires an 8-bit address to identify a
particular table entry. The present invention allows such a table to be addressed using 4-bit data blocks in the input data stream. For each received 4-bit data block in the input data stream, a determination is made as to whether that block
corresponds to a predetermined key value. If a given input block does not correspond to the predetermined key value, the 4-bit input block is combined with a previously-stored 4-bit pallet identifier to generate an 8-bit address into the look-up table.
The pallet identifier specifies one of 16 different 16-entry pallets within the 256.times.16 look-up table. If the given input block does correspond to the key value, a new 4-bit pallet identifier is stored. The new pallet identifier may be contained
within a data block which immediately follows the key value
block in the data stream. The new pallet identifier is then used in combination with subsequent 4-bit data blocks in the stream to generate 8-bit addresses into the look-up table. This arrangement provides substantial improvements in table
addressing efficiency and is particularly well-suited for use in graphics processors which generate graphics data using color look-up tables.
Another aspect of the invention relates to a technique for permitting simultaneous utilization of two system clocks in applications in which certain processing system elements utilize one system clock operating at a non-integer multiple of
another system clock used by other processing system elements. For example, a processing system may include a video decoder and/or an NTSC encoder which operate with a first clock at 27 MHz. The processing system may also include an ASIC processor
operating with a second clock at 40.5 MHz. A synchronous phase detector is used to generate a clock enable signal suitable for use in a pipeline structure to facilitate data transfer between the different elements of the processing system. An exemplary
circuit may include two or more D-type flip-flops or other data storage devices. The first clock signal is applied to a clock input of a first data storage device, and the second clock is applied to a data input of the first data storage device. The
second clock is also applied to a clock input of at least one additional data storage devices connected in series with the first data storage device. The output of the first data storage device is applied to the data input of a second data storage
device, the output of the second is applied to the data input of a third, and so on. The clock enable signal is provided at the output of the fourth data storage device. The clock enable signal includes phase information extracted from the first and
second clock signals, and is suitable for use in driving one or more multiplexers in a pipeline structure or other state-based logic device to thereby allow data transfer between an element of the processing system operating at the first clock rate and
an element operating at the second clock rate.
Another aspect of the invention involves a differential video data encoding technique which utilizes a reduced number of bits per pixel to encode chroma and luma components of a video data stream. In an exemplary embodiment, a 4-bit absolute
code is determined for a given 8-bit luma or chroma component in the data stream. The determined absolute code is indicative of a particular one of a plurality of ranges into which the given component falls. The given component is encoded using the
determined absolute code if the absolute code produces a lower encoding error than a 4-bit delta code which encodes the component as a difference relative to a previously-encoded component. If the delta code produces a lower encoding error than the
determined absolute code, the given component is encoded using the delta code. In a situation in which the given component is the first component of its type on a line of video, an absolute code may be used regardless of whether or not the absolute code
produces a higher encoding error than the delta code. The number of 4-bit absolute codes may be selected as fourteen, such that each absolute code specifies one of fourteen possible ranges into which the given component may fall. The remaining two
4-bit delta codes specify whether a predetermined value should be added to or subtracted from the value of a previously-encoded component. Alternatively, the number of 4-bit absolute codes may be selected as eleven, such that each absolute code
specifies one of eleven possible ranges into which the given component may fall. The remaining five 4-bit delta codes specify whether a first predetermined value should be added to or subtracted from the value of the previously-encoded component,
whether a second predetermined value should be added to or subtracted from the value of the previously-encoded component, or whether the given component should be encoded using the same value as the previously-encoded component. Numerous other
arrangements of absolute and delta codes could also be used.
Another aspect of the invention relates to a single-buffered display capture technique. The display capture technique eliminates a "tearing" problem which arises when a top portion of a displayed video image is from a current frame, while a
bottom portion of the displayed image is from a previous frame. An exemplary embodiment includes an apparatus for processing a video signal in a processing system, wherein the video signal including a sequence of frames each having an even field and an
odd field. The apparatus includes a video capture circuit which receives the video signal from a video source, and a video display circuit which has an input coupled to an output of the video capture circuit. The video capture circuit captures a first
set of lines in an even field of the video signal during a time period in which the video display circuit displays a second set of lines in the even field. The video capture circuit also captures the second set of lines in an odd field of the video
signal during a time period in which the video display circuit displays the first set of lines in the odd field. The video capture circuit utilizes an odd-numbered decimation factor to determine the first and second sets of lines from all lines in the
even and odd fields.
Another aspect of the invention involves a technique for utilizing a hardware register to prevent interference between simultaneously-running processes which attempt to access certain processing hardware such as a drawing acceleration engine. In
a exemplary embodiment, a method and apparatus are provided for controlling access of a plurality of processes to a graphics engine in a graphics processor. The graphics processor or other device such as a CPU associated with the processor includes a
register with an acquire bit portion and a process identifier portion. When a given process requests access to the graphics engine, a determination is made as to whether the acquire bit of the register is set. A set acquire bit indicates that some
process has already been granted access to the engine. If the acquire bit is not set, the requesting process is granted access to the engine, and its process identifier is stored in the process identifier portion of the register. If the acquire bit is
already set when the given process requests access to the engine, the identifier for that process is compared to the identifier stored in the process identifier portion of the register. If the identifiers match, the requesting process is granted access. The lack of a match between the identifiers indicates that a different process has previously been granted access to the engine, and the requesting process is therefore denied access to the engine. When a process granted access to the engine no longer
requires access, the acquire bit is cleared. This hardware-based sharing mechanism allows multiple processes to share common state-sensitive graphics hardware such as a drawing acceleration engine.
Another aspect of the invention is directed to a memory arbitration technique which allows multiple hardware functions implemented in a single ASIC to utilize a single shared memory unit or multiple shared memory units. The memory arbitration
technique establishes a priority among multiple memory access requestors which is particularly well-suited for use in a set top box processing system. This aspect of the invention significantly reduces the complexity of a set top box or other processing
system in that separate memory controllers are eliminated a nd memory conflicts are considerably reduced. An exemplary embodiment provides a method of arbitrating between a plurality of memory access requests received from a plurality of processing
elements in a set top box processing system. The processing elements include a transport stream demultiplexer, a host central processing unit and a graphics processor. The method involves the steps of receiving the memory access requests from the
processing elements, and permitting the processing elements to access a shared memory in accordance with an established priority. The established priority assigns a higher priority to the graphics processor than to the host central processing unit, and
may be in the order of graphics processor, transport stream demultiplexer, and central processing unit. In an embodiment in which the plurality of processing elements includes an asynchronous transfer mode (ATM) processing element, the established
priority may assign the lowest priority to the memory access requests of the ATM processing element.
Another aspect of the invention involves an ATM segmentation and reassembly (SAR) device which provides efficient transfer of ATM cell data between a set top box or other processing system and an ATM network. The SAR device provides filtering of
a stream of received ATM cells by comparing the virtual channel indicators (VCIs) of the incoming cells with a plurality of indicators stored in a receive VCI table. A given cell is accepted if the VCI for that cell matches one of the stored indicators. At least one additional stored indicator may be used as a hash table to provide a matching function for a number of additional VCIs. If the VCI for the given received cell does not match one of the stored indicators in the receive VCI table, at least a
portion of the VCI for that cell can be used as a bit index into the hash table provided by the additional stored indicator. The given received cell is accepted if the hash table bit designated by the portion of the VCI used as a bit index has a
predetermined value. The indicator table may be implemented as a 16.times.16 random access memory table in which the first 15 entries represent VCI values to be accepted by a receiver, and the last entry represents a 16-bit hash table such that the four
least significant bits of a given received VCI are used as a bit index into the table. A given received cell is discarded if its VCI does not match one of the identifiers stored in the identifier table and if its corresponding hash table bit does not
have the predetermined value.
The SAR device also provides an improved technique for storing received ATM cells which facilitates the reassembly process. An exemplary embodiment uses a receive ring which stores an array of pointers. Each of the pointers specifies the
address of a cell buffer suitable for storing an ATM cell. Received ATM cells are first filtered to determine if the cells should be accepted in the SAR device. As noted above, this filtering may be based on a comparison of the incoming cell VCIs with
entries in a receive VCI table. When a given cell is accepted, a pointer retrieved from the receive ring is used to determine the address of a cell buffer in which that cell will be stored. Host CPU software directing the operation of the SAR device
periodically services the receive ring to prevent overflow. The periodic servicing of the receive ring may be triggered by a flag indicating that all or most available receive ring pointers are already in use. The host CPU software then services the
receive ring by sequentially stepping through the ring entries and linking the pointer for each stored cell into a chain of pointers maintained for the VCI on which that stored cell was received. The pointers which are linked into a chain are removed
from the receive ring and replaced with pointers to empty cell buffers so that additional receive cells can be processed and stored. When an end-of-frame indicator is detected in a cell received on a given VCI, the host CPU software uses the pointers in
the chain maintained for that VCI, as well as any pointers for that VCI remaining in the receive ring, to reassemble an AAL5 frame. A cumulative frame cyclic redundancy code (CRC) is computed using dedicated hardware in a CRC processor. The host CPU
software uses the pointers to direct the CRC processor to each cell of the frame in turn, until the full frame CRC is computed. The frame is then accepted or rejected based on a comparison of the computed full frame CRC with the CRC field of the frame
trailer. An accepted frame may be passed to upper protocol layers for additional processing, and is eventually written to application buffers such that the cell buffers and corresponding pointers are free to be reused for subsequently-received cells.
The cell buffers and corresponding pointers for a rejected frame may be made immediately available for reuse.
The SAR device also provides improved segmentation by utilizing a host CPU to direct the transmission of stored cells in accordance with an array of pointers stored in a transmit ring. In one possible embodiment, host CPU software directs the
realignment of stored cell data using dedicated hardware in the form of a CRC processor. The CRC processor computes a full frame CRC as it carries out the cell data realignment under the direction of the host CPU software. The full frame CRC is
retrieved from the CRC processor and inserted into an AAL5 trailer in the last cell of a frame to be transmitted. The host CPU software then loads the transmit ring with pointers identifying the cell buffers containing the ATM cetls of the frame to be
transmitted. A transmitter in the SAR device retrieves a pointer from the transmit ring and then retrieves the corresponding ATM cell identified by the pointer. The transmitter then transmits the retrieved cell to the ATM physical layer interface via a
UTOPIA port. The host software periodically services the transmit ring to return pointers for already-transmitted cells to a list of available pointers, and to load the transmit ring with pointers for new cells to be transmitted. The software loads the
pointers such that a quality of service transmission rate established for a given VCI is not exceeded, and may direct the interleaving of cells from multiple VCIs as well as the insertion of pointers to null cells into the transmit ring.
These and other features and advantages of the present invention will become more apparent from the accompanying drawings and the following detailed description.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of an exemplary processing system in accordance with the present invention.
FIGS. 2A-2D illustrate different graphics processing modes which may be implemented in the processing system of FIG. 1.
FIG. 3A is a block diagram of an exemplary graphics prescaler in accordance with the invention and suitable for use in the processing system of FIG. 1.
FIG. 3B is a flow diagram illustrating the operation of the exemplary graphics prescaler of FIG. 3A.
FIG. 4A illustrates an exemplary 256.times.16 color look-up table (CLUT) divided into sixteen separate pallets and suitable for use in a dynamic CLUT alteration technique which may be implemented in the processing system of FIG. 1.
FIG. 4B shows an input data stream and a corresponding converted data stream suitable for use with a dynamic CLUT alteration technique.
FIG. 4C is a schematic diagram of an exemplary circuit implementation of a dynamic CLUT alteration technique.
FIG. 4D is a flow diagram illustrating an exemplary dynamic CLUT alteration technique.
FIG. 5A is a schematic diagram illustrating an exemplary synchronous phase detector in accordance with the present invention and suitable for use in the processing system of FIG. 1.
FIG. 5B is a timing diagram illustrating the operation of the clock enable circuit of FIG. 5A.
FIG. 6A is a block diagram illustrating a data transfer pipeline utilizing a clock enable signal generated in the synchronous phase detector of FIG. 5A.
FIG. 6B is a timing diagram illustrating the operation of the data transfer pipeline of FIG. 6A.
FIG. 7A shows the correspondence between bytes and pels in an exemplary video data stream to be encoded in accordance with a differential encoding technique of the present invention.
FIG. 7B is a flow diagram illustrating a video date encoding technique in accordance with the invention.
FIGS. 8A and 8B are block diagrams illustrating an exemplary video processing system in which a single-buffered display capture technique may be implemented in accordance with the invention.
FIG. 9A shows an exemplary register configured to provide a hardware-based drawing acceleration engine sharing function in accordance with the present invention.
FIG. 9B is a flow diagram illustrating the operation of an exemplary sharing function using the register of FIG. 9A.
FIG. 10 is a block diagram illustrating an exemplary system suitable for implementing asynchronous transfer mode (ATM) segmentation and reassembly (SAR) functions in accordance with the invention.
FIG. 11A is a block diagram of an exemplary SAR receiver in accordance with the present invention.
FIG. 11B is a flow diagram illustrating the input filtering and storage functions performed in an ATM reassembly operation.
FIG. 11C shows an exemplary receive ring portion of memory suitable for use in an ATM reassembly operation.
FIG. 11D is a flow diagram illustrating the cyclic redundancy code (CRC) calculation and AAL5 framing functions of an ATM reassembly operation.
FIGS. 12A-12H illustrate an exemplary ATM reassembly operation in accordance with the present invention.
FIG. 13 is a block diagram of a CRC processor suitable for use in ATM segmentation and reassembly operations.
FIG. 14A is a block diagram of an exemplary SAR transmitter in accordance with the invention.
FIG. 14B is a flow diagram illustrating a portion of an exemplary segmentation operation in accordance with the invention.
DETAILED DESCRIPTION OF THE INVENTION
The present invention will be described in a number of different sections as set forth in the following brief outline.
______________________________________ 1. Set Top Box Processing System 2. Graphics Processor 2.1 Square Pixel Aspect Ratio 2.2 Graphics Modes 2.3 Alpha Prescaler 2.4 Dynamic Color Look-up Table (CLUT) 3. Clock Circuitry 3.1 Synchronous
Phase Detector 3.2 Multiple Clock Pipeline Structure 4. Video Data Encoding 5. Single-Buffered Display Capture 6. Register-Based Process Sharing 7. Memory Arbitration 8. ATM Segmentation and Reassembly (SAR) Features 8.1 General Description 8.2
Reassembly 8.3 Segmentation ______________________________________
Although illustrated herein in conjunction with exemplary set top box processing applications, the present invention is more generally applicable to numerous other video, audio, graphics and/or communication applications. For example, the ATM
SAR features of the present invention may be utilized in any application requiring an efficient interface to an ATM network, and the multiple clock enable circuit may be utilized in any application in which it is desirable for different portions of a
device or system to utilize one or more additional clocks which are non-integer multiple versions of a first clock. The term "set top box" as used herein should therefore be construed broadly to include any video, audio, graphics and/or communications
processing device or system. Furthermore, although illustrated in conjunction with MPEG-2 transport streams, the invention is more broadly applicable to packet-based data streams generated in accordance with standards other than MPEG-2. These other
standards include, for example, the video and audio portions of the CCITT H.320 standard, and the audio coding standards of MPEG-1 and Dolby AC-3. The term "transport stream" as used herein should therefore be understood to refer to any packet-based
digital data stream which includes video, audio and/or other types of data, or various combinations thereof.
1. Set Top Box Processing System
FIG. 1 is a block diagram of an exemplary set top box processing system 10 in accordance with the present invention. The processing system 10 includes a network interface module (NIM) 12 which receives an input signal via a network port 14. The
NIM 12 may serve as an interface to a cable, telephone or computer network. For example, the input signal may an RF signal supplied from a multichannel multipoint distribution service (MMDS) to the processing system 10 at a remote user site using
conventional transmission techniques. Other exemplary signal distribution techniques suitable for use with the present invention include switched digital video (SDV), hybrid fiber/coax (HFC), direct broadcast satellite (DBS) and digital subscriber loop
(DSL). The input signal is demodulated or otherwise processed in a physical layer interface 16. Portions of the demodulated input signal are supplied from an output interface 18 to an ASIC processor 20 over data interface line 22. An MPEG-2 transport
stream portion of the demodulated input signal is applied over line 24 to the processor 20. The portions of the demodulated input signal passing over lines 22 and 24 may be further processed by a digital video broadcast (DVB) descrambler 24 within the
ASIC 20. The DVB descrambler 24 could alternatively be arranged external to the ASIC 20. The MPEG-2 transport stream represents hierarchically-organized compressed video, audio and other program data, and is described in greater detail in A.
Wasilewski, "MPEG-2 Systems Specification: Blueprint for Network Interoperability," Comm. Tech., February 1994, which is incorporated by reference herein. The MPEG-2 standard was developed by the International Standards Organization (ISO) Moving
Picture Experts Group (MPEG) and is documented in ISO/IEC DIS 13818, which is incorporated by reference herein. Other portions of the demodulated input signal, as well as control signals for the NIM 12, may be supplied over a bus 28 connected to the
interface 18. The bus 28 is also connected to the ASIC processor 20.
A central processing unit (CPU) 30 is connected to bus 28, and may be implemented as a Motorola MC68306 processor operating at 16 MHz. Many alternative CPUs are suitable for use in processing system 10, including, for example, other CPUs in the
MC68xxx series, as well as CPUs in the PowerPC 40x series. Also connected to bus 28 is a Flash read-only memory (ROM) 36 which may have a memory capacity on the order of 512 Kbytes. Other elements which may be connected to bus 28 but are not shown in
FIG. 1 include a modem and an optional SIMM socket for expansion of dynamic random access memory (DRAM). The modem may be used to communicate with external telephone, computer or cable network communication channels. The ASIC processor 20 includes a
CPU interface 32 through which the processor 20 and other elements connected thereto communicate with the CPU 30. The processing system 10 further includes a DRAM 40 which communicates via bus 28 with the ASIC processor 20. The DRAM 40 may have a
memory capacity on the order of 512 Kbytes, although it should be noted that the capacity of DRAM 40, Flash ROM 36 and other memory devices in processing system 10 may vary depending upon the memory requirements of a given application. As will be
described in greater detail below, the DRAM 40 is generally used to support CPU operations, as well as the video, graphics and ATM communication processing functions of the processor 20. The processor 20 includes a DRAM controller 42 which may control
some or all of the DRAM 40 using control signals supplied via line 44. The processor 20 also includes an MPEG-2 demux 50 which receives an MPEG-2 transport stream from the NIM output interface 18 via line 26 and generates therefrom one or more MPEG-2
elementary data streams.
The MPEG-2 transport stream supplied via line 24 will now be described in more detail. A given transport stream associates related elementary data streams for a given program or programs such that the elementary streams can be extracted, decoded
and presented together in a coherent fashion. Each elementary data stream represents a stream of MPEG-2 encoded audio, video or other data. An MPEG-2 transport stream generally includes a sequence of fixed-length 188-byte transport packets. A
transport packet of the PES-bearing type includes a payload which carries a portion of a longer packetized elementary stream (PES) packet, where a PES packet includes elementary stream data for a given program as well as corresponding timing,
identification and control information. All PES-bearing transport packets with a common packet identifier (PID) carry elementary stream data for a single common elementary stream and no other. The payload portion of the transport packet will thus
include elementary stream data from a corresponding PES packet if the transport packet is of the PES-bearing type. The transport packet may also be of the program specific information (PSI) type or the private data type.
Each transport packet also includes a one-byte sync pattern and a three-byte prefix, and may include a variable-length adaptation field. The adaptation field may include, for example, program clock reference (PCR) and encryption key management
information. The sync byte is a fixed pattern which permits identification of the beginning of each transport packet, and is 47xH in the MPEG-2 standard. The prefix includes a thirteen-bit packet identifier PID which, as noted above, identifies the
elementary stream supplying the transport packet payload. The transport packet prefix also includes two adaptation field control bits which indicate whether the corresponding transport packet includes a payload with no adaptation field, an adaptation
field with no payload, or both an adaptation field and a payload. The prefix further includes a packet error indicator bit, a payload unit start indicator bit, a transport priority bit, two transport scrambling control bits and a four-bit continuity
counter. Additional detail regarding MPEG-2 transport packets may be found in the above-cited ISO reference.
The MPEG-2 demux 50 may provide a number of additional functions, including video and audio decoder control, PSI table parsing, PCR clock recovery, and private data capture which supports multiple simultaneous PIDs. It should be noted that the
MPEG-2 demux 50 may be configured in the manner described in U.S. patent application Ser. No. 08/585,109 entitled "Transport Stream Decoder/Demultiplexer for Hierarchically Organized Audio-Video Streams," which is assigned to the assignee of the
present invention and incorporated by reference herein. Although not illustrated in FIG. 1, transport stream recording and playback features may be provided in processing system 10 in the manner described in U.S. patent application Ser. No. 08/566,283
entitled "Recording and Playback of Audio-Video Transport Streams," which is assigned to the present assignee and incorporated by reference herein.
Elementary video streams from the MPEG-2 demux 50 are supplied to an MPEG-2 video decoder 52, while elementary audio streams from the demux 50 are supplied to an MPEG-2 audio decoder 54. The processor 20 may manage small ring buffers in DRAM 40
for each of the elementary streams. The decoders 52, 54 convert the elementary streams into decoded video and audio data signals, respectively, using conventional techniques. The video decoder 52 utilizes a DRAM 56 to perform MPEG-2 video decoding
operations, and may be configured to support full main-profile-at-main-level (MP@ML) MPEG-2 decoding as defined by the above-cited ISO/IEC 13818-2 specification. The memory capacity of the DRAM 56 may be on the order of 2 Mbytes. The decoded video
signal from decoder 52 is supplied to a graphics processor 60 in the ASIC processor 20 and utilized in graphics overlay operations to be described in greater detail below. The graphics processor 60 in processor 20 combines the decoded video signal with
one or more graphics signals and supplies a combined digital video output signal to an NTSC encoder 64 via line 65. The NTSC encoder 64 converts the digital video signal to an analog video signal suitable for display on a television or other display
monitor connected to a composite video output 67.
The MPEG-2 audio decoder 54 may be configured to support the Musicam Audio Layer II as defined by the ISO/IEC 11172-3 specification, including all single and dual channel modes. Multiple sample rates such as 32 KHz, 44.1 KHz and 48 KHz may be
supported. The decoded audio signal from decoder 54 is supplied to a pulse-code modulation (PCM) audio processor 62 in the processor 20. The PCM audio processor 62 in processor 20 combines the decoded audio signal with one or more PCM audio signals and
supplies a combined digital audio signal to an audio digital-to-analog converter (DAC) 68 via line 69. The audio DAC 68 converts the combined digital audio signal into an analog audio signal which may be supplied to a speaker or other audio output
device connected to stereo output 70. The PCM audio feature allows uncompressed PCM audio to be mixed with decoded MPEG audio so that it is possible to, for example, play sound effects while decoding an MPEG program. The analog video and audio output
signals are also supplied directly to an RF modulator 72 which may be configured to modulate the analog video and/or audio onto one or more RF carrier signals suitable for application to an RF input of a television, video cassette recorder (VCR) or other
device connected to RF output 74. An RF bypass input 76 is connected to the RF modulator 72 and is used, for example, to allow an input analog video signal from another source to be supplied directly to a television monitor.
The processing system 10 includes a smartcard interface 80 connected to the processor 20. The smartcard interface includes a smartcard socket for receiving a smartcard. The smartcard socket may be configured in accordance with the ISO 7816
standard, which is incorporated by reference herein, and may utilize a smartcard of the type known as NagraVision.TM. available from Nagra+ of Switzerland. Numerous alternative smartcards are well known in the art and may also be used. The smartcard
interface 80 and corresponding smartcard may be part of a conditional access service (CAS) compliant with ISO/IEC 13818-1, ISO 7816 and the Digital Video Broadcast (DVB) recommendations. The CAS system utilizes the MPEG-2 demux 50 in processor 20 to
identify entitlement management messages (EMMs) and entitlement control messages (ECMs) in an incoming MPEG-2 transport stream. The EMMs are typically addressed to the decoders 52, 54 and indicate whether the decoders are entitled to receive program
data transmitted on a given input signal channel or channels. The EMMs may also be used to specify an entitlement time range, or event signaling information such as near video on demand (NVOD)/pay-per-view (PPV) billing credits, return channel access
schedules, parental control information or custom application-defined events. A given EMM may contain an encrypted service key which is used to decrypt subsequent ECMs. The service keys are changed at a relatively low rate, typically on the order of
days or months. The ECMs are addressed to the decoders 52, 54 and contain encrypted control words (CWs) which are changed at a relatively frequent rate, typically on the order of seconds. The EMMs and ECMs identified in demux 50 are queued by processor
20 in DRAM 40 for transmission through the smartcard interface 80 to the smartcard. A direct memory access (DMA) technique may be used to implement this transfer. The smartcard stores a secret key for the processing system 10 and uses the secret key to
decrypt an encrypted service key and thereby authenticate the EMM information. The decrypted service key is then used to decrypt the encrypted CWs which are supplied to the DVB descrambler 26 for use in decoding portions of an entitled program. Any
event EMMs may be transferred to an event queue for processing by the CPU 30.
The processing system 10 includes an infrared (IR) receiver 82 which receives a control signal from a remote control device in a conventional manner. The system 10 is also configured to include an IR transmitter 85 which supplies an output IR
signal to an IR output 86. The output IR signal may be used to control the operation of or otherwise communicate information to other devices within the vicinity of the processing system 10. For example, the IR transmitter 85 may be used to communicate
with a VCR in conjunction with an electronic programming guide to facilitate VCR programming.
An interface to an asynchronous transfer mode (ATM) communication network is provided in system 10 using an ATM segmentation and reassembly (SAR) device 90 contained within processor 20. The operation of the SAR device 90 will be described in
greater detail below. The ATM SAR device 90 may interface directly with a UTOPIA port for connection to an ATM network via a physical layer (PHY) device such as a synchronous optical network (SONET) interface. The term UTOPIA refers to a standard
handshake/data transfer protocol defined by the ATM Forum for communication between an ATM layer device, such as an ATM SAR device, and a physical layer device, such as a SONET interface. The UTOPIA port may be included within the processor 20 or
elsewhere in the processing system 10. Alternative
protocols could also be used to interface processor 20 with an ATM network. The ATM SAR capability facilitates implementation of the processing system 10 in applications based on switched digital video (SDV) architectures. As will be described
in greater detail below, an ATM SAR device in accordance with the present invention alleviates processing bottlenecks by utilizing a shared memory approach and an appropriate allocation of hardware and software responsibility for ATM processing
operations.
It should be noted that many of the elements of processing system 10 which are shown outside the ASIC processor 20 may in alternative embodiments be incorporated into the processor 20. For example, one possible alternative arrangement could
incorporate the video decoder 52, the audio decoder 54 and the NTSC encoder 64 into the ASIC processor 20. Of course, numerous other alternative arrangements of the illustrated elements may also be utilized.
2. Graphics Processor
The set top box processor 20 includes a graphics processor 60 which can be configured to support a variety of graphics modes and resolutions. An exemplary embodiment may support a background plane, a decoded video plane, a graphics plane and a
hardware cursor. The graphics plane may be arranged to support multiple resolutions of pixel size and aspect ratio, including square pixels, multiple color modes, and multiple levels of alp | | |
