A depletion type MISFET is formed on a surface of the semiconductor substrate, MISFET including a source region, a drain region, a channel region between the source and drain regions, a gate insulating film on the channel region, and a gate electrode on the gate insulating film. An impurity diffusion region is formed in a surface layer of the semiconductor substrate. An interconnect electrically connects the gate electrode and impurity diffusion region. A p-n junction is reversed biased when a voltage sufficient for cutting off the MISFET is applied to the gate electrode relative to the channel region, an electric path between the impurity diffusion region and the channel region is made non-conductive. Pads are connected to the gate electrode, source region, and drain region.
A method for manufacturing a DRAM device includes the step of implanting phosphor at a specified dosage and heat treating the implanted phosphor for diffusion thereof to form source/drain regions, and implanting fluorine into the source/drain regions and heat treating the implanted fluorine for diffusion thereof. The resultant DRAM memory cell has a larger data storage capability due to lower junction leakage current caused by vacancy type defects formed in the metallurgical junction between the source/drain regions and the channel region.
In a logic area, impurities are doped into the gate electrode and the source/drain diffusion regions of a MIS transistor. Thereafter in a memory cell area, word lines are patterned, source/drain regions are formed, and contact holes are formed. Side wall spacers of the MIS transistor in the logic area are made of silicon oxide. A semiconductor device of logic-memory can be manufactured by a reduced number of manufacture processes while the transistor characteristics are stabilized and the fine patterns in the memory cell are ensured.
A charging sensor is provided to detect charging signal during the manufacturing process of integrated circuits and various semiconductor devices. In one embodiment, the charging sensor includes a charging-sensitive insulator layer and complementary elements designed to effectively provide an indicative potential drop across the charging sensitive insulator.
A semiconductor device (10,50) is disclosed which can accommodate a negative voltage on its source using a P-type substrate (12) which is connected to ground potential. A first embodiment illustrates a device which can handle high voltage applications as well as a negative voltage applied to the source. A drain contact region (29) is recessed by a dimension (X) from a first insulated region (18). The dimension (X) provides for an optimum distance for high voltage applications while avoiding lateral surface punch-through. A second embodiment illustrates a gate structure (52) having a shape which surrounds a drain contact region (62) and accommodates a high voltage application while also eliminating the lateral surface punch-through. The drain contact region (62) is formed in a P-type region (20) centered inside the gate structure (52).
A semiconductor device includes a semiconductor substrate of a first conductivity type, a well of the first conductivity type formed in the semiconductor substrate, a transistor formed in the well, a diffusion region of a second conductivity type formed in the semiconductor substrate so as to cover a lateral side and a bottom edge of the well, a terminal formed on the semiconductor substrate at an outside part of the diffusion region, and a conductive region contacting with the well, the well being in ohmic contact with the terminal via the conductive region and the semiconductor substrate, the conductive region having an impurity concentration level exceeding an impurity concentration level of the semiconductor substrate.
