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Description  |
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FIELD OF THE INVENTION
This invention relates to memory circuits and, more particularly, to fully synchronous pipelined random access memory circuits.
BACKGROUND
Many high performance systems require a memory that operates with a fast system clock. Some designers use synchronous random access memories ("RAMs") to meet this system requirement. For example, some synchronous static RAMs (SRAMs) are
available which use registers or latches to temporarily store the address and control. These SRAMs use a "pipeline" scheme whereby the address to be accessed is provided during one cycle and, during the next sequential cycle, the data is provided on the
data bus. For example, during a read operation, the address from which data is to be read is provided on the nth cycle and the data read from the SRAM is provided on the data bus on the (n+1)th cycle. For write operations, there
are SRAMs that provide the address, control and data during the same cycle and there are designs where address and control are provided on the nth cycle and data is provided on the (n+1)th cycle.
The speed of the SRAM is increased because the set-up and hold time for a register or latch is typically much shorter than the time to access the main array of the SRAM (the difference typically being several nanoseconds). The result is to break
the operations into shorter cycles. On the (n+1)th cycle, the register or latch provides the stored address to the SRAMs main array along with the data to be written to the stored address, meeting the set-up and hold times for writing to the SRAM's main
array. Because of the reduced set-up and hold time for the address and data on the (n+1)th cycle, the SRAM's cycle time, as viewed at the pins of the device, can be significantly reduced. As a result, the frequency of the system clock can be increased.
One problem with conventional SRAMs is that, typically, trying to intermix reads and writes in a high speed system causes a cycle to be "lost" when a memory writee is immediately followed by a memory read (i.e., bus turnaround). Generally, a
cycle is lost on turnaround because the structure of these RAMs requires an extra cycle to make sure that all of the data is written into the memory before a read operation can be performed. For example, if a write operation is followed by a read
operation from the same address, a lost cycle is needed so that the "new" data will be written to the specified address before the read operation is performed on the data stored at the same address. In systems where bus turnaround occurs frequently, the
lost cycles on bus turnaround can significantly reduce the bandwidth of the system. With conventional synchronous SRAMs, the same problem can exist.
SUMMARY
According to the present invention, a fully synchronous pipelined RAM with no lost cycles on bus turnaround is provided (i.e., the RAM is capable of performing a read operation during any clock cycle or a write operation during any clock cycle
without limitation).
One embodiment of the present invention, an SRAM, includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and control signals during any cycle referred to as the nth cycle. During a
write operation on the nth cycle, the corresponding write data to be written into the SRAM is provided during the next, (n+1)th, cycle. During the nth cycle, the logic circuit causes the previously stored write data to be written from the input circuit
into the memory. The new write data associated with the address and control signal received on the nth cycle is received into the input circuit on the (n+1)th cycle. The write data and the address remain in the input circuit during any intervening read
operations.
In this embodiment, when performing a read operation, the logic circuit compares the address of the read operation to the address of the most recent write operation. If the addresses match, then the SRAM outputs the data stored in the input
circuit; however, if the addresses do not match, the SRAM outputs the data stored in the memory corresponding to the requested read address.
In another embodiment of the present invention, an SRAM includes an input circuit, an output circuit, a logic circuit and a memory. In this embodiment, the input circuit is coupled to receive a memory address and control signals during any cycle
referred to as the nth cycle. The output circuit includes a register to store data read from the memory which is read during the (n+1)th cycle. Data will then be provided out of the output circuit on the next, (n+2)th, cycle.
The logic circuit causes the write data to be stored in a first data register in the input circuit two clock cycles after receipt of the write address and control signals. This data will move through the two-stage pipeline in the input circuit
during intervening read operations. Thus, write data is written into the memory during the second write operation after the data has been received in the input circuit. These operations and their associated variations will be more fully understood in
accordance with the detailed description taken with the drawings.
When performing a read operation, the logic circuit compares the address of the read operation to the addresses of the previous two write operations. If the read address matches one of the write-addresses stored in the input circuit, then the
SRAM outputs to the output circuit the data corresponding to the matched address from the input circuit to the output circuit; if the read address matches both of the write-addresses stored in the input circuit, then the SRAM outputs to the output
circuit the data corresponding to the most recently written matched address from the input circuit to the output circuit; however, if the addresses do not match, the SRAM outputs to the output circuit the data stored in the memory corresponding to the
requested read address.
This invention will be more fully understood in accordance with the following detailed description taken with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a block diagram of one embodiment of the present invention using a single stage pipeline.
FIG. 2 shows a more detailed diagram of the embodiment of FIG. 1.
FIG. 3 shows a timing diagram illustrating the operation of the embodiment of FIG. 2.
FIG. 4 shows a block diagram of another embodiment of the present invention using a two-stage pipeline.
FIGS. 5A, 5B and 5C show timing diagrams illustrating the operation of the embodiment of FIG. 4.
FIGS. 6A (comprising sheets 6A-1 and 6A-2) and 6B (comprising sheets 6B-1 and 6B-2) illustrate the logic states of certain components and terminals shown in FIG. 7 for two different read/write sequences applied to the structure shown in FIG. 7 in
the double pipelined (i.e., two-stage pipeline) mode.
FIG. 7 (comprising sheets 7-1 and 7-2) shows a schematic block diagram of an embodiment of the present invention capable of operating in either a single pipeline or two-stage pipeline configuration.
FIGS. 7A and 7B (comprising sheets 7B-1 and 7B-2) show the embodiment of FIG. 7 modified for single stage pipeline and two-stage pipeline operation, respectively.
FIGS. 8A and 8B show timing waveforms for two sequences of read/write signals applied to the structure of FIG. 7 operating in the single pipeline mode and dual pipeline mode, respectively.
FIG. 9 (comprising sheets 9A and 9B) shows an embodiment of this invention suitable for implementation in an integrated circuit chip.
FIGS. 10A and 10B show timing waveforms illustrating the operation of the embodiment of FIG. 9 in the two-stage pipeline mode for two different sequences of read/write signals.
FIG. 10C shows timing waveforms illustrating the operation of the embodiment of FIG. 9 in the one stage pipeline mode for one sequence of read/write signals.
DETAILED DESCRIPTION
FIG. 1 shows a simplified block diagram of a single pipeline SRAM 100 according to one embodiment of the present invention. Although this embodiment utilizes SRAM memory cells, this invention also can be embodied using DRAM memory cells. SRAM
100 includes a memory 110 connected to control logic 120, which is connected to an input circuit 130. Input circuit 130 is coupled to receive address, control, and clock signals from a processor or controller (not shown) on input address bus 131, input
control lead or bus 132, and input clock lead 134, respectively. Input data bus 133 is connected to control logic 120.
A read operation is performed as follows. During the nth cycle, the processor or controller (not shown) provides to SRAM 100 an address to be read on bus 131. The processor or controller also indicates a read operation by asserting (i.e. taking
high) the read/write signal transmitted on control lead or bus 132. During the (n+1)th cycle, control logic 120 compares the address of the read operation stored in input circuit 130 to the address stored in control logic 120 during the most recent
write operation. If the addresses match, then control logic 120 outputs the data stored in the control logic 120 corresponding to the most recent write operation via an output buffer 140; however, if the addresses do not match, control logic 120
outputs, via output port D0 and buffer 140, the data stored in SRAM memory 110 corresponding to the address of the read operation. Because the data is read from control logic 120 when a read operation sequentially follows a write operation and the
address of the data to be read corresponds to the address to which the last received write data is to be written, no extra cycle is needed to write the data into memory 110 before it can be read as in conventional synchronous SRAMs. As a result, lost
cycles are eliminated during bus turnaround, thereby increasing the bandwidth of a system using SRAM 100.
A write operation is performed as follows. The processor or controller (not shown) provides to SRAM 100 an address on bus 131 during an nth cycle. The processor or controller also indicates a write operation by deasserting (i.e. taking low) a
read/write signal transmitted on input control lead or bus 132. Control lead 132 may be replaced by a bus which can then carry other control signals, such as a chip enable signal and a chip select signal. The processor provides on the (n+1)th cycle the
corresponding data on bus 133 (called "write data") to be written to SRAM 110 during the (n+2)th write cycle at the address on bus 131 during the nth cycle.
Input circuit 130 receives and stores the address and control on one cycle and the corresponding write data on the next following cycle. Input circuit 130 receives the address and control and input logic 120 receives the write data with a much
shorter set up and hold time relative to a typical SRAM memory, thereby allowing SRAM 100 to have a shorter cycle time.
During the (n+1)th cycle, control logic circuit 120 causes the write data stored in control logic 120 during the previous write operation to be written into SRAM memory 110 and stored there at the address also stored in control logic 120
associated with that write data.
Logic circuit 120 simply holds the write data and write address during any intervening read operations.
FIG. 2 shows an embodiment of the SRAM system 100 in FIG. 1. Like reference numerals are used between drawings for like structures. SRAM system 100 includes registers A1, A3, R1 and D3. Register A3 and register D3 each includes an enable input
lead 200-1 and 200-2 respectively. When register A3 or register D3 receives a logic low signal on enable input lead 200-1 or enable input lead 200-2, respectively, register A3 or register D3 will operate as a conventional register. However, register A3
and register D3 each will not alter the stored information on its output bus 205 or 221, respectively, while a logic high signal is received on enable input lead 200-1 or enable input lead 200-2, respectively.
Registers A1, R1 and D3 are respectively coupled to receive the address signals via bus 131, the read/write control signal via bus 132 and the data signals from the Data I/O input port via bus 133. The output bus 201 of register A1 is connected
to the input bus 202 of register A3 and to the H input port 203 of a multiplexer 204. The output bus 205 of register A3 is connected to the L input port 206 of multiplexer 204. The output port 207 of multiplexer 204 is connected to the address port of
memory 110. Thus, multiplexer 204 operates to provide either the address stored in register A1 or the address stored in register A3 to memory 110 to identify in memory 110 either the address from which read data is to be read or the address to which
write data is to be written.
Multiplexer 204 is controlled by the read/write signal stored in register R1, which signal register R1 provides to the select input lead of multiplexer 204 via line 208. The stored read/write signal, when asserted (i.e. high) to indicate a read
operation, causes multiplexer 204 to pass the output signals of register A1 to the address port of memory 110.
Conversely, the stored read/write signal, when deasserted (i.e. low) to mean a data-write operation, causes multiplexer 204 to pass the output signals of register A3 to the address port of memory 110; the write data signals in register D3 are
already applied to the Data-In port of memory 110.
In addition, the stored read/write signal, when deasserted to indicate a write operation, enables register A3 to store the output address signals from register A1 and further enables new write data to be stored in register D3, this new write data
being associated with the address signals being transferred from address register A1 to address register A3. All register storage is on the rising clock edge where the clock signal transitions from low-to-high.
FIG. 3 shows a timing diagram exemplifying a series of read and write operations. With reference to FIGS. 2 and 3, a read operation is performed as follows. In the nth cycle, the read/write signal into register R1 is asserted (i.e. goes high)
on lead 132. Register R1 receives and stores the asserted read/write signal on the rising edge of the clock signal at the end of the nth cycle (i.e. the start of the (n+1)th cycle) and outputs the asserted read/write signal at the beginning of the
(n+1)th cycle. At the same nth cycle as the read/write signal into register R1 is asserted, register A1 receives the read address on input bus 131, and on the next rising edge of the clock signal at the start of the (n+1)th cycle, stores in, and outputs
from register A1 the address a.sub.1 to be accessed. At the same time, address a.sub.0 stored in register A1 is transferred to register A3 since the diagram shows a write cycle at the beginning of the nth cycle. The asserted (i.e. high) read/write
signal output from register R1 at the beginning of the (n+1)th cycle causes multiplexer 204 to pass address a.sub.1 in register A1 to memory 110. No write data is associated with the read operation.
Assuming that the read/write signal applied on the input lead 132 to control register Ri during the (n-1)th cycle represented a write operation, then the address a.sub.0 stored in address register A1 during the nth cycle represents the address in
memory 110 to which data d.sub.0 is to be written. Data d.sub.0, data to be written into SRAM 110 at address a.sub.0, is applied at the Data I/O port during the nth cycle and is stored in data register D3 on the low-to-high transition of the clock
signal at the end of the nth cycle.
SRAM system 100 also includes a comparator 211 having an input bus 212 connected to output port 201 of register A1 and another input bus 213 connected to output port 205 of register A3. Consequently, during the first part of the (n+1)th cycle
comparator 211 compares the requested read address a.sub.1 (the address stored in register A1) to the address a.sub.0 of the location in memory to which data d.sub.0 in register D3 will be sent on the next write clock cycle (this location is at the
address a.sub.0 stored in register A3). When comparator 211 detects that addresses a.sub.1 and a.sub.0 match, then the read operation is reading from the address a.sub.0 (stored in register A3) to which data d.sub.0 in register D3 is to be written in
the next write operation. The updated data d.sub.0 stored in register D3 and corresponding to address a.sub.0 in register A3 has not yet been written into memory 110; rather, the updated data d.sub.0 is passed to the input port 218 of mux 217.
The output lead 215 of comparator 211 is connected to select lead 216 of multiplexer 217. Multiplexer 217 has an H input port 218 connected by bus 221 to the output port 219 of register D3. Multiplexer 217 has an L input port 220 connected to
the Data-Out port of memory 110.
During the read operation in the (n+1)th cycle, if comparator 211 detects that address a.sub.1 in register A1 does not match address a.sub.0 in register A3, then multiplexer 217 selects the Data-Out port of memory 110 (i.e., data d.sub.1 stored
in memory 110 corresponding to address a.sub.1) and outputs this data on bus 220 through mux 217 and through buffer 140 to the Data I/O bus. However, if comparator 211 detects that address a.sub.1 does match address a.sub.0 in register A3, then during
the (n+1)th cycle, multiplexer 217 passes the output signals d.sub.0 on buses 221 and 218 from the data out port 219 of register D3 to the Data I/O bus through
buffer 140.
Referring to FIGS. 2 and 3, a write operation is performed as follows. In this example, the read/write signal (i.e. R/W*) is deasserted (i.e. taken low) during the (n+1)th cycle to indicate a write operation is to take place in the (n+2)th
cycle. On the next transition of the clock signal from low-to-high at the end of the (n+1)th cycle and the beginning of the (n+2)th cycle, register R1 receives, stores and outputs the deasserted read/write signal. Consequently, a low signal on the
select input line 208 of multiplexer 204 causes mux 204 to pass on bus 207 to the address port of SRAM 110 the output signals on bus 205 representing the address a.sub.0 stored in register A3 (which is the address in SRAM memory 110 to which the data
d.sub.0 stored in register D3 as a result of the previous write operation during the nth cycle is to be written).
Write enable circuit 210 controls the actual writing of data into SRAM 110. Circuit 210 is enabled by the deasserted (i.e. low) write signal as is register D3, thereby causing memory 110 to receive at the Data-In port, the data signals d.sub.0
on buses 221 and 218 from register D3 on the next low clock signal (SRAM 110 is enabled by write enable circuit 210 to write data d.sub.0 on the low clock signal during cycle (n+2)). During cycle (n+2) the data d.sub.0 in register D3 will be written
into the location in memory 110 defined by the address a.sub.0 in register A3. Also, during cycle (n+2), register A1 receives, stores and outputs the address a.sub.2 to which to-be-received data d.sub.2 applied to the Data I/O terminal during the
(n+2)th cycle is to be written in SRAM 110 on the next write cycle.
Pulse circuit 210 provides a delayed self timed high-low-high pulse after a low-to-high clock signal after waiting the required time to receive the stored deasserted read/write signal from register R1 via a line 200. This pulse causes memory 110
to store at the address a.sub.0 (received from register A3 via multiplexer 204) the data d.sub.0 received at the Data-In port of memory 110. The Data-In port of memory 110 is connected by buses 218 and 221 to the output port 219 of register D3, which
outputs data d.sub.0 (the data from the previous write operation associated with address a.sub.0).
In addition, during the (n+2)th cycle, data d.sub.2 is applied to the Data I/O terminal and thus to the input port of register D3. Data d.sub.2 corresponds to address a.sub.2 loaded in register A1 during the low-to-high transition of the clock
signal signifying the end of the (n+1)th cycle and the beginning of the (n+2)th cycle. During the (n+2)th cycle, the read/write signal is asserted (i.e. goes high) to indicate that a read operation associated with address a.sub.3 will take place during
cycle (n+3).
At the end of cycle (n+2), on the low-to-high transition of the clock signal, register D3 stores data d.sub.2 associated with address a.sub.2. Address a.sub.2 in register A1 is transferred to register A3 also at the end of cycle (n+2).
In the same manner as described above, the read/write signal asserted during the end of cycle (n+2) is stored in register R1 on the low-to-high transition of the clock signal at the start of cycle (n+3). Register Ri provides the asserted
read/write signal on output lead 200 to disable pulse circuit 210, on output lead 200-2 to disable data register D3 and on output lead 200-1 to disable address register A3. Thus, on the low-to-high transition of the clock signal at the start of the
(n+4)th cycle, address a.sub.2 remains in address register A3.
Then, during the cycle (n+3), the read/write signal is deasserted (i.e. goes low), thereby indicating the start of another write operation during upcoming cycle (n+4). Thus, during cycle (n+4) the output signal from register R1 is low thus
enabling pulse circuit 210. Pulse circuit 210 provides a pulse to write data d.sub.2 from register D3 into the location in memory 110 at address a.sub.2 in address register A3 during cycle (n+4) a delayed time after the low-high transition of the clock
signal.
Referring back to cycle (n+2), during this cycle the read/write signal is asserted, thereby indicating a read operation. This read operation sequentially follows a write operation (i.e., bus turnaround), which would result in a lost cycle in
conventional synchronous SRAMs because the conventional synchronous SRAM must write the data into the main memory before this data can be read during the read operation. However, in memory circuit 100, the operation of comparator 211 and multiplexer 217
provides the data requested by the read operation (specified by an address a.sub.3 in register A1) if this data is d.sub.2 (the address a.sub.2 to which this data d.sub.2 is to be written is stored in register A3 at the start of cycle (n+3)) without
first writing this data d.sub.2 into memory 110, thereby eliminating the lost cycle. Accordingly, an SRAM memory system 100 will have higher system bandwidth relative to the conventional synchronous SRAM system because there is no lost cycle on bus
turnaround.
FIG. 4 shows a block diagram of another embodiment of the present invention. In the embodiment of FIG. 4 each of the elements disclosed therein is identical to the elements disclosed in FIG. 1 with the exception that buffer 140 has been replaced
by register 440. Register 440 allows the fully synchronous SRAM of this invention to be used in the system with two pipeline delays as opposed to the single pipeline delay system shown in FIG. 1. Thus, an output signal from SRAM 110 is passed through
control logic 120 on bus 443 to register 440 and there stored to be read out of register 440 on bus 444 in response to a clocking signal brought to register 440 on leads 441 and 442 from an external clock (not shown) on the next following clock cycle.
The remainder of the structure shown in FIG. 4 at the level of abstraction depicted is identical to that shown in FIG. 1 and operates in essentially the same manner as described above in conjunction with FIGS. 1, 2 and 3 but with two cycle delays
associated with data to be written into SRAM 110 and with additional registers and logic required to implement the two-stage pipeline delay.
FIGS. 5A, 5B, and 5C, respectively, illustrate the double pipeline read sequence for reading information from the memory of FIG. 7, the double pipe write sequence for writing information into the memory at a specified address, and an illustrative
double pipe read and write sequence as applied over a period of clock cycles illustrated as 0-8 (FIG. 5C).
As shown in FIG. 5A, the double pipe read requires the presence on the input bus to the first address register of an address containing information to be read on the first cycle, the read out from the SRAM of the information at the specified
address in the SRAM in the second cycle and then, on the third clock cycle, the storage of this data in a system register and the reading out from the system register of this data.
The double pipe write shown in FIG. 5B requires the presence on the input bus to an address register of an address of the location in memory to which data is to be written on the first cycle, a delay for the second cycle during which time the
address on the input bus is transferred into the address register. This is followed by a third cycle during which write data to be written into the memory is applied to the input bus of a first data register. This data is written into the first data
register in the system on the fourth cycle.
FIG. 7 illustrates a fully synchronous SRAM system utilizing the principles of this invention. As a feature of this circuit, read and write cycles can be intermixed without bus turnaround cycles for a read cycle following a write cycle. Edge
triggered registers (i.e. registers which load signals previously applied to their input buses on a low-to-high clock signal transition) are used to store address, data and control signals. The unique bus turnaround capability of this invention is
achieved using internal edge-triggered flip flops and various gating and controlling logic.
In the single pipeline delay mode, read data to be output from the system is available at the Data I/O bus on the next clock cycle after the read address and control signals are presented to the input leads. A separate asynchronous output
structure is available to solve high speed timing problems on read cycles should such problems arise.
Data for write cycles is presented to the Data I/O bus on the cycle following the cycle in which the address and control signals are presented to the address input bus and the control signal input bus, respectively. Thus, whether read or write,
the data signals are always one cycle delayed from address and control signals. But the address and control signals are applied to the memory simultaneously in proper timing to ensure that the data is written to or read from the proper cells in the
memory.
The structure shown in FIG. 7 is particularly useful in very high speed digital applications. For example, digital signal processing memories for recursive or nonrecursive filters or digital integrators can move data on every clock cycle. ATM
switches can have access to data cells continuously without dead cycles. High speed cache memory systems can implement read cycles or write cycles on every clock cycle without interruption caused by the memory component. In many high speed
applications, this can result in a speed improvement of up to fifty percent (50%), for example.
In the circuit block diagram schematic shown in FIG. 7, the following abbreviations are used.
______________________________________ NAME PINS FUNCTION ______________________________________ Address 17 or more Address inputs. Word select in the SRAM. Data 8 Data inputs/outputs. CLK 1 Clock input. All operations (except write to SRAM
710) execute on the low-to-high transitions. R/W* 1 Read/Write input. CS* 1 Chip select input. When active (low), the chip is enabled. When high, the chip is deselected and all functions are disabled. CEN* 1 Clock enable input. CpEN 1 When
active (low), the chip is enabled. When not active (high), all register operations are disabled. Data still appears on the output data bus if the last valid operation was a read and data still appears on the input bus to be written into memory
if the last valid operation was a write. OE* 1 Output enable input. An asynchronous signal. When low, the output buses are enabled. When high, the output buses are high impedance. Sgl/Dbl* 1 When high, the data in or out is delayed by one clock
cycle. When low, the data in or out is delayed by two clock cycles. Cnt/Load* 1 When low, the address register will load the address presented on the address pins. When high, the address register will load the value currently held in the
register as modified by the +1 logic; linear or other mapping. Vdd 6 Plus voltage inputs. Vss 7 Ground inputs. ______________________________________
With the above definitions of terms, the schematic block diagram shown in FIG. 7 will now be described. The SRAM system of FIG. 7 has the unique property of being able to read or write on every cycle with no dead cycles. The data, read or
write, is always delayed by one or two clock cycles (a function of whether a single clock cycle delay or a two clock cycle delay is used) compared to the address and control signals.
The circuit of FIG. 7 is capable of operating either as a single pipeline structure (one clock cycle delay) or a double pipeline structure (two clock cycle delay). Thus, when the signal SGL/DBL* (denoted as S/D* in FIG. 7) is high, the data
in/out is delayed by one clock cycle. When SGL/DBL* is low, the data in/out is delayed by two clock cycles.
In the schematic block diagram of FIG. 7, comparators have been given the numbers 701-i, where i represents a particular comparator, multiplexers have been given the numbers 703-i, where i represents a particular multiplexer, address registers
have been given the numbers 704-i where i represents a particular address register, read/write (R/W*) control signal registers have been given the numbers 707-i where i represents a particular control signal register, chip enable registers have been
numbered 708-i, and two sets of registers whose uses will be described shortly have been numbered 709-i and 710-i, where i equals 1 or 2. Inverters have been numbered 705-i and logic gates, delays, an edge detector, an output buffer and other
miscellaneous components have been given the numbers 706-i. Item 702 is a pulse generator. To avoid cluttering the drawing, leads and terminals have not been numbered.
SINGLE PIPELINE OPERATION
In the single pipeline configuration (i.e. one clock delay version) of the structure of FIG. 7, S/D* is high. The operation of the structure of FIG. 7 in the single pipeline mode (i.e. single clock delay mode) will be explained in light of the
timing waveforms of FIG. 8A.
While time has been shown as starting at to in FIG. 8A, this choice is arbitrary. In any event, time to should be understood to represent some arbitrary time during the operation of the circuit and not the start time of the circuit. This is
shown in FIG. 8A by the notation n, n+1, n+2, . . . n+8 placed above the arbitrary times t.sub.0, t.sub.1, t.sub.2, . . . t.sub.8, respectively to show that FIG. 8A describes the nth through (n+8)th cycles of operation, where n is a selected integer.
Period t.sub.0
During period t.sub.0 the address signals a.sub.0 and the R/W* signal are supplied t.sub.0 appropriate input buses to the circuit. These signals are clocked into address register 704-1 and control register 707-1 on the low-to-high clock
transition at the end of period t.sub.0 and the start of period t.sub.1. During period t.sub.0 (and all subsequent time periods of operation of this circuit of FIG. 7) the select input signal Cnt/Load on the select input lead to mux 703-1 is low thereby
allowing the address signals a.sub.0 applied to the address input bus of mux 703-1 to pass through mux 703-1 to the D input bus of address register 704-1. Register 704-1 is enabled by CpEn* low. Simultaneously OR gate 706-1, enabled by chip select
signal CS* low, allows the R/W* signal to pass through OR gate 706-1 to the D input lead into register 707-1.
Mux 703-3 has the FLIP signal applied to its gate. This FLIP signal is low because the signal S/D*, applied to one input lead of inverter 705-4 is high (indicating one clock cycle delay). The output signal from inverter 705-4 is low so long as
the system is operating in the single pipeline
mode. Therefore the output signal from AND gate 706-7 will be low regardless of the states of the input signals W1 and R2 on the other two input leads to AND gate 706-7.
Similarly, OR gate 706-5 receives input signals on three input leads. The first input lead is connected to the output lead of mux 703-8. Because mux 703-8 is controlled by the high S/D* signal, mux 703-8 passes the CS1* signal through the S
input lead. Since CS1* is low, OR gate 706-5 will have a low input signal on the input lead connected to the output lead of mux 703-8. Chip enable signal CpEn*, applied to the middle input lead of OR gate 706-5, is also low to enable the chip
containing the circuit of FIG. 7 to operate. The third input lead to OR gate 706-5 is connected to the output lead of mux 703-6. The select input lead of mux 703-6 is driven by the high S/D* signal for the single pipeline mode. The two input leads to
mux 703-6 carry the R1 and R2 signals, respectively. Because the low output signal from mux 703-8 and the low CpEn* signal enable OR gate 706-5, the signal passed by mux 703-6 is transferred through OR gate 706-5 to the output lead of OR gate 706-5.
This signal, depending on whether it is low or high enables or disables, respectively, data registers 709-1 and 709-2 and address registers 704-3 and 704-4. When R1 is high, the output signal from OR gate 706-5 is high and when R1 is low the output
signal from OR gate 706-5 is low. R1 is low only when a write signal is stored in control register 707-1. Thus, the output signal from OR gate 706-5 enables data storage registers 709-1 and 709-2 and address registers 704-3 and 704-4 only when the R1
signal is low indicating a write.
Referring to FIG. 8A as well as FIG. 7, the particular address a.sub.0 to which data d.sub.0 will be written is stored in register 704-1 on the rising edge of the clock signal between time period t.sub.0 and time period t.sub.1, one clock cycle
before the data d.sub.0 associated with address a.sub.0 is applied to the Data I/O lead of the circuit.
During time period t.sub.0, a write signal w.sub.-1 is shown as stored in register 707-1.
Period t.sub.1
If the R/W* signal is a write signal (i.e. low) during time t.sub.0, then the output lead R1 of register 707-1 will have a low level signal during period t.sub.1. The output signal W1 from inverter 705-1 will be high during period t.sub.1.
The output address signal a.sub.0 at address register 704-1 is applied to the H input bus of multiplexer 703-4. However the select input of mux 703-4 is driven by the low R1 signal from register 707-1 and therefore the address signal a.sub.0
applied to the H input bus of mux 703-4 is not passed through mux 703-4.
On the low-to-high transition of the clock signal at start of period t.sub.1, data d.sub.-1 is transferred into data register 709-1.
During period t.sub.1, a new address a.sub.1 is applied to the input bus to register 704-1. Simultaneously, data d.sub.0 is applied through the Data I/O pin to the input bus to data register 709-1. Register 709-1 is enabled to receive and store
data by the low write signal R1 on the Q output lead of control register 707-1 (corresponding to the signal w.sub.0 in FIG. 8A) applied through the S input lead of mux 703-6 to one input lead of OR gate 706-5 to produce a low enable signal on the enable
input leads E of data registers 709-1 and 709-2 and address registers 704-3 and 704-4. At the low-to-high transition of the clock signal between periods t.sub.0 and t.sub.1, the control signal in register 707-1 during period t.sub.0 is transferred to
register 707-2. The output signal on the Q output lead from register 707-2 is inverted in inverter 705-2 to yield output signal W2 which is high or low depending on the state of register 707-2.
The address a.sub.-1 in register 704-1 during period t.sub.0 is transferred to address registers 704-2 and 704-3 during the low-to-high transition of the clock signal at the start of period t.sub.1. This latter transfer occurs through the S
input bus of mux 703-2, the select input signal to which is S/D* which is high for the single pipeline mode of operation. The states of the select inputs on muxes 703-3 and 703-4 remain as they were during period t.sub.0.
Mux 703-3 passes the output address a.sub.-1 on the Q output bus from register 704-3 and on the L input bus to mux 703-3 to the L input bus of mux 703-4 (selected by signal R1 from control register 707-1 being low) and from there to the address
port of memory 710. Thus, the address of memory 710 to which data d.sub.-1 in data register 709-1 will be written is a.sub.-1. Simultaneously, the low FLIP signal is applied to the select input lead of mux 703-5, the output bus of which is connected to
the Data-In port of memory 710. Consequently mux 703-5 passes the data signal d.sub.-1 from data register 709-1 to the L input bus of mux 703-5. Because W1 is high when R1 is low and HOLD is high (HOLD is the inverted low output signal on the Q output
lead from register 710-1, the input signal to which is low CpEn*), AND gate 706-3 is enabled. The output signal from AND gate 706-3 goes high in response to the delayed clock signal being applied to one input lead of AND gate 706-3 through delay 706-2.
This clock signal causes write enable circuit 706-4 to produce a low pulse to enable the write input to SRAM 710. Consequently during the period t.sub.1, the data d.sub.-1 is read into and stored at the location in SRAM memory 710 given by address
a.sub.-1 because the control signal in register 707-1 during time t.sub.0 is a write signal w.sub.-1.
Period t.sub.2
On the low-to-high transition of the clock signal at the end of period t.sub.1 and the start of period t.sub.2, address a.sub.1 is entered into register 704-1 and address a.sub.0, previously in register 704-1, is transferred to registers 704-2 (a
"don't care") and 704-3, replacing the address a.sub.-1 formerly in these two registers. Simultaneously, write signal w.sub.1 is stored in control register 707-1. Data d.sub.0 is transferred into data register 709-1 and data d.sub.1 which corresponds
to the address a.sub.1 stored in address register 704-1, is placed on the input bus to data register 709-1 from Data I/O terminal. Data d.sub.-1 is transferred from register 709-1 to register 709-2 (a "don't care").
During period t.sub.2 the clock signal is transmitted through delay 706-2 and, since HOLD and W1 are both high, causes AND gate 706-3 to cause write enable circuit 706-4 to enable SRAM 710 to write into memory the data d.sub.0 stored in data
register 709-1 at the address a.sub.0 stored in address register 704-3. Address a.sub.0 stored in address register 704-3 is transmitted to the address port of SRAM 710 on the L input bus of mux 703-3 and the L input bus of mux 703-4.
Thus, by the end of period t.sub.2, data d.sub.0 has been placed in memory 710 at the address a.sub.0, and data d.sub.1, corresponding to address a.sub.1 placed in address register 704-1 at the start of period t.sub.2, has been placed on the
input bus to data storage register 709-1.
Period t.sub.3
At the start of the next time period t.sub.3, the data d.sub.1 is transferred into data storage register 709-1 and the data d.sub.0 previously in this data register is transferred to data register 709-2 (a "don't care").
During period t.sub.3, data d.sub.1 is transferred into SRAM memory 710 through the L input bus of mux 703-5 to the Data-In port of memory 710 and stored in memory 710 at the address a.sub.1 stored in register 704-3 during the low-to-high
transition of the clock signal at the start of period t.sub.3. Address a.sub.1 is transmitted through the L input bus of mux 703-3 and the L input bus of mux 703-4 into the address port of memory 710 to control the location to which the data d.sub.1 in
data register 709-1 is written.
Period t.sub.4
On the low-to-high transition of the clock signal at the start of period t.sub.4, data d.sub.1 is transmitted into data register 709-2 (a "don't care") replacing the data d.sub.0 previously in that register. Simultaneously control signal W3 is
placed in control register 707-1 and the control signal W2 previously in register 707-1 is transferred to control register 707-2. Thus, signals Rl and R2 remain low reflecting the write control signals stored in registers 707-1 and 707-2, respectively.
Data d.sub.2 is transferred into data register 709-1 replacing the data d.sub.1 simultaneously transmitted into data register 709-2. The address a.sub.2 previously in address register 704-1 is transferred into address registers 704-2 (a "don't care")
and 704-3. The address a.sub.2 is transmitted through the L input bus of mux 703-3 to the L input bus of mux 703-4 to the address port of SRAM 710. Simultaneously, data d.sub.2 in data register 709-1 is transmitted through the low input bus of mux
703-5 to the Data-In port of SRAM 710. Thus, data d.sub.2 will be written to address a.sub.2 in SRAM 710 upon the low write enable signal from enable circuit 706-4 being applied to the write enabled port of SRAM 710 during period t.sub.4.
Address a.sub.4 is placed on the input bus to address register 704-1 and R/W* signal r.sub.4, denoting a read operation, is placed on the input bus to control register 707-1 during period t.sub.4. The Q output lead of register 707-1 still
carries a low level signal because write signal w.sub.3 is stored in register 707-1 and W1 from inverter 705-1 remains high. W2 remains high because the previous low write signal w.sub.2 is transferred into control register 707-2 causing the output
signal W2 from inverter 705-2 to remain high. The R1 input signal on the S input lead to mux 703-6 remains low thereby enabling data registers 709-1 and 709-2 and address registers 704-3 and 704-4.
Period t.sub.5
On the low-to-high transition of the clock signal at the start of period t.sub.5, address a.sub.4 is transferred into address register 704-1 and address a.sub.3 previously in this register is transferred into address registers 704-2 (a "don't
care") and 704-3. Data d.sub.3 is passed into data register 709-1 and write signal r.sub.4 is transferred into control register 707-1 thereby causing signal R1 to go high. Thus, the signal W1 from inverter 705-1 goes low. The write signal r.sub.4 in
control register 707-1 causes mux 703-4 to select the signals on the H input bus for transfer to the output bus connected to the address port of SRAM 710. Thus, the address a.sub.3 stored in address register 704-3 is not transferred to the address port
of SRAM 710. Rather, the address a.sub.4 stored in address register 704-1 is transmitted through the H input bus of mux 703-4 to the address port of SRAM 710.
Because a read control signal is now stored in control register 707-1, a read operation is to be carried out during time period t.sub.5. If the address a.sub.4 stored in address register 704-1 does not equal the address a.sub.3 stored in address
register 704-3, then the output signal Eq3 from comparator 701-2 will be low. Thus, mux 703-13 will be activated to pass the data out at the address a.sub.4 in SRAM 710 through the L input bus of mux 703-13 to the S input bus of output mux 703-12
activated by the high level signal S/D*. This output signal will then be transmitted through output buffer 706-9 to the Data I/O pin.
The signal R1 going high passes through mux 703-6 on the S input lead and then through OR gate 706-5 to cause OR gate 706-5 to produce a high level output signal thereby disabling data registers 709-1 and 709-2 and address registers 704-3 and
704-4. Consequently, at the start of the next time period, these registers will be disabled and will retain the contents which they held during period t.sub.5.
Should, however, the address a.sub.4 equal the address a.sub.3 stored in address register 704-3, Eq3 will be high. High Eq3 will cause the data d.sub.3 in data register 709-1 to be transmitted through the H input bus of mux 703-13 and from there
to the S input bus of mux 703-12 to the output buffer 706-9 and from there to the Data I/O port. Thus, the data stored in data register 709-1 does not have to be written into SRAM 710 when address a.sub.4 equals address a.sub.3 but rather can be read
out of the system to the Data I/O bus.
Address signal a.sub.5 and control signal r.sub.5 are applied to the input bus and lead, respectively, of address register 704-1 and control register 707-1.
Period t.sub.6
On the low-to-high transition of the clock signal at the start of time period t.sub.6, address a.sub.5 is loaded into address register 704-1. Address a.sub.4 previously in this register is transferred to address register 704-2 (a "don't care").
Address a.sub.3 previously in address register 704-3 remains in address register 704-3, because register 704-3 has been disabled by a high level output signal from OR gate 706-5.
Simultaneously, read control signal r.sub.5 is loaded into control register 707-1 and the previous read control signal r.sub.4 in register 707-1 is transferred to register 707-2. Thus, signal R1 is high and signal W1 is low. Because OR gate
706-5 produced a high level output signal during period t.sub.5, data register 709-1 is disabled. Thus, throughout period t.sub.6 data register 709-1 retains the data d.sub.3 previously placed in that register at the start of time period t.sub.5.
Control signal r.sub.5 indicates that a read of the data at address a.sub.5 is to be carried out on SRAM memory 710 during period t.sub.6. Address a.sub.5 from register 704-1 is transmitted through the H input bus of mux 703-4 selected by R1
being high to the address port of SRAM 710. If address a.sub.5 does not equal address a.sub.4 in data register 704-2, then the signal Eq2 from comparator 701-1 will be low. If a.sub.5 does not equal a.sub.3 stored in data register 704-3, the signal Eq3
will also be low. Thus, the data in SRAM 710 at address a.sub.5 will be transmitted through the Data Out port and through the L input bus of mux 703-13 to the S input bus of mux 703-12 and from there through output buffer 706-9 to the Data I/O bus from
the system.
If, however, the address a.sub.5 equals the address a.sub.3 stored in data register 704-3, then the output signal Eq3 from comparator 701-2 will be high. Eq3 high will cause the data d.sub.3 stored in data register 709-1 to be transmitted
through the H input bus of mux 703-13 to the S input bus of mux 703-12 and from there through buffer 706-9 to the Data I/O port. Buffer 706-9 is enabled during period t.sub.6 as it was during period t.sub.5 by the high R1 output signal from control
register 707-1.
Address a.sub.6 and control signal w.sub.6 are applied to the input bus and input lead, respectively, of address register 704-1 and storage register 707-1.
Period t.sub.7
On the low-to-high transition of the clock signal at the start of period t.sub.7, address a.sub.6 is loaded into address register 704-1. Address a.sub.5 previously in address register 704-1 is loaded into address register 704-2. However address
a.sub.3 previously in address register 704-3 remains in address register 704-3 because this register has been disabled by the high output signal from OR gate 706-5.
Simultaneously, write control signal w.sub.6 is transferred into control register 707-1. Read signal r.sub.5 previously in control register 707-1 is transferred to control register 707-2. Thus, the signal R1 goes low and W1 goes hig | | |
