Method and apparatus for controlling the data rate of a clocking circuit

Claims

What is claimed is:

1. A data rate control circuit, comprising:

a first clock line receiving a first clock signal that transitions between a pair of logic levels, the first clock signal having a first frequency and a first phase;

a second clock line receiving a second clock signal, the second clock signal having the first frequency and a second phase;

a switching circuit coupled to the second clock line to receive the second clock signal, the switching circuit operative in a first mode to couple the second clock line to an output line, and operative in a second mode to couple a steady state voltage to the output line; and

a clocking circuit coupled to the first clock line and the output line, the clocking circuit structured to clock on transitions of the first clock signal to both logic levels in response to receiving the second clock signal on the output line, and clocking on transitions of the first clock signal to only one logic level in response to receiving the steady state voltage on the output line.

2. The data rate control circuit of claim 1 wherein the clocking circuit comprises a circuit that performs a predetermined function each time the clocking circuit clocks.

3. The data rate control circuit of claim 1 wherein the clocking circuit comprises a shift register.

4. The data rate control circuit of claim 1 wherein the clocking circuit comprises a counter latch.

5. The data rate control circuit of claim 1 wherein the one logic level comprises a logic one logic level.

6. The data rate control circuit of claim 1 wherein the clocking circuit comprises a circuit that clocks on transitions of the first clock signal to a logic one logic level in response to receiving the steady state voltage on the output line.

7. The data rate control circuit of claim 1 wherein the clocking circuit comprises a circuit that clocks on only transitions of the first clock signal to a logic zero logic level in response to receiving the steady state voltage on the output line.

8. The data rate control circuit of claim 1 wherein the steady state voltage comprises a positive voltage.

9. The data rate control circuit of claim 1 wherein the steady state voltage comprises zero volts.

10. The data rate control circuit of claim 1 wherein the switching circuit comprises a switching element.

11. The data rate control circuit of claim 1 wherein the switching circuit comprises an antifuse.

12. The data rate control circuit of claim 1 wherein the switching circuit comprises a transistor.

13. A data rate control circuit, comprising

a first clock line receiving a first clock signal, the first clock signal having a first frequency, a first phase, a first edge, and a second edge;

a second clock line receiving a second clock signal, the second clock signal having the first frequency, a second phase, and a first duty cycle;

a duty cycle changing circuit coupled to the second clock line and having an output line, the duty cycle changing circuit receiving the second clock signal and a reference signal, the reference signal having a second duty cycle, the duty cycle changing circuit operative in a first mode to couple the second clock line to the output line, and operative in a second mode to couple the reference signal to the output line; and

a clocking circuit coupled to the first clock line and the output line, the clocking circuit structured to clock on both edges of the first clock signal in response to receiving a signal on the output line having the first duty cycle and structured to clock on only one edge of the first clock signal in response to receiving a signal on the output line having the second duty cycle.

14. The date rate control circuit of claim 13 wherein the first duty cycle is 50% and the second duty cycle is 100%.

15. The date rate control circuit of claim 13 wherein the first duty cycle is 50% and the second duty cycle is 0%.

16. The data rate control circuit of claim 13 wherein the clocking circuit comprises a circuit that performs a predetermined function each time the clocking circuit clocks.

17. The data rate control circuit of claim 13 wherein the clocking circuit comprises a shift register.

18. The data rate control circuit of claim 13 wherein the clocking circuit comprises a counter latch.

19. The data rate control circuit of claim 13 wherein the first edge is a rising edge and the second edge is a falling edge.

20. The data rate control circuit of claim 13 wherein the first edge is a rising edge and the second edge is a falling edge, and the clocking circuit comprises a circuit that clocks on only the rising edge of the first clock signal in response to receiving a signal on the output line having the second duty cycle.

21. The data rate control circuit of claim 13 wherein the first edge is a rising edge and the second edge is a falling edge, and the clocking circuit comprises a circuit that clocks on only the falling edge of the first clock signal in response to receiving a signal on the output line having the second duty cycle.

22. The data rate control circuit of claim 13 wherein the duty cycle changing circuit comprises a switching element.

23. The data rate control circuit of claim 13 wherein the duty cycle changing circuit comprises an antifuse.

24. The data rate control circuit of claim 13 wherein the duty cycle changing circuit comprises a transistor.

25. A data rate control circuit, comprising

a first clock line receiving a first clock signal, the first clock signal having a first frequency, a first phase, a first edge, and a second edge;

a second clock line receiving a second clock signal, the second clock signal having the first frequency, and a second phase;

a frequency changing circuit coupled to the second clock line and having an output line, the switching circuit receiving the second clock signal and a reference signal, the reference signal having a second frequency, the switching circuit operative in a first mode to couple the second clock line to the output line, and operable in a second mode to couple the reference signal to the output line; and

a clocking circuit coupled to the first clock line and the output line, the clocking circuit structured to clock on both edges of the first clock signal in response to receiving a signal on the output line having the first frequency, and clocking on only one edge of the first clock signal in response to receiving a signal on the output line having the second frequency.

26. The date rate control circuit of claim 25 wherein the first frequency is a positive number.

27. The date rate control circuit of claim 25 wherein the second frequency is zero.

28. The data rate control circuit of claim 25 wherein the clocking circuit comprises a circuit that performs a predetermined function each time the clocking circuit clocks.

29. The data rate control circuit of claim 25 wherein the clocking circuit comprises a shift register.

30. The data rate control circuit of claim 25 wherein the clocking circuit comprises a counter latch.

31. The data rate control circuit of claim 25 wherein the first edge is a rising edge and the second edge is a falling edge.

32. The data rate control circuit of claim 25 wherein the first edge is a rising edge and the second edge is a falling edge, and the clocking circuit comprises a circuit that clocks on only the rising edge of the first clock signal in response to receiving a signal on the output line having the second frequency.

33. The data rate control circuit of claim 25 wherein the first edge is a rising edge and the second edge is a falling edge, and the clocking circuit comprises a circuit that clocks on only the falling edge of the first clock signal in response to receiving a signal on the output line having the second frequency.

34. The data rate control circuit of claim 25 wherein the frequency changing circuit comprises a switching element.

35. The data rate control circuit of claim 25 wherein the frequency changing circuit comprises an antifuse.

36. The data rate control circuit of claim 25 wherein the frequency changing circuit comprises a transistor.

37. A data rate control circuit, comprising:

a first clock line receiving a first clock signal, the first clock signal having a first frequency, a first phase, a first edge, and a second edge;

a second clock line receiving a second clock signal, the second clock signal having the first frequency and a second phase;

a fuse having a first end and a second end, the first end coupled to the second clock signal line;

an antifuse having a first side and a second side, the first side coupled to a steady state voltage source and the second side coupled to the second end of the fuse; and

a clocking circuit coupled to the first clock line and to the second side of the antifuse, the clocking circuit structured to clock on both edges of the first clock signal in response to receiving the second clock signal through the fuse, and clocking on only one edge of the first clock signal in response to receiving the steady state voltage through the antifuse.

38. The data rate control circuit of claim 37 wherein the clocking circuit comprises a circuit that performs a predetermined function each time the clocking circuit clocks.

39. The data rate control circuit of claim 37 wherein the clocking circuit comprises a shift register.

40. The data rate control circuit of claim 37 wherein the clocking circuit comprises a counter latch.

41. The data rate control circuit of claim 37 wherein the first edge is a rising edge and the second edge is a falling edge.

42. The data rate control circuit of claim 37 wherein the first edge is a rising edge and the second edge is a falling edge, and the clocking circuit comprises a circuit that clocks on only the rising edge of the first clock signal in response to receiving the steady state voltage on the output line.

43. The data rate control circuit of claim 37 wherein the first edge is a rising edge and the second edge is a falling edge, and the clocking circuit comprises a circuit that clocks on only the falling edge of the first clock signal in response to receiving the steady state voltage on the output line.

44. A data rate control circuit, comprising:

a first clock line receiving a first clock signal, the first clock signal having a first frequency, a first phase, a first edge, and a second edge;

a second clock line receiving a second clock signal, the second clock signal having the first frequency, a second phase, a third edge, and a fourth edge;

a switching circuit coupled to the first clock line and the second clock line, the switching circuit having a first output line and a second output line, the switching circuit receiving the first clock signal on the first clock line, and the second clock signal on the second clock line, the switching circuit operative in a first mode to couple the first clock line to the first output line and to couple the second clock line to the second output line, and operative in a second mode to couple the first output line to a steady state voltage and to couple the second output line to a third clock signal, the third clock signal having the first frequency, a third phase, a fifth edge and a sixth edge;

a clocking circuit coupled to the first output line and the second output line, the clocking circuit structured to clock when a signal on the first output line is a relatively high voltage and also structured to clock when a signal on the second output line is a relatively low voltage.

45. A memory device having an address bus, comprising:

a memory array circuit comprising a plurality of memory cells arranged in rows and columns, a plurality of row lines, and at least one digit for each column of memory cells; and

an addressing circuit coupled to the address bus and the memory array circuit, the addressing circuit adapted to receive row and column addresses on the address bus and activate a corresponding memory cell in the array responsive to a command word, the addressing circuit having a data rate control circuit, the data rate control circuit comprising:

a first clock line receiving a first clock signal that transitions between a pair of logic levels, the first clock signal having a first frequency and a first phase;

a second clock line receiving a second clock signal, the second clock signal having the first frequency and a second phase;

a switching circuit coupled to the second clock line to receive the second clock signal, the switching circuit operative in a first mode to couple the second clock line to an output line, and operative in a second mode to couple a steady state voltage to the output line; and

a clocking circuit coupled to the first clock line and the output line, the clocking circuit structured to clock on transitions of the first clock signal to both logic levels in response to receiving the second clock signal on the output line, and clocking on transitions of the first clock signal to only one logic level in response to receiving the steady state voltage on the output line.

46. The memory device of claim 45 wherein the clocking circuit comprises a circuit that performs a predetermined function each time the clocking circuit clocks.

47. The memory device of claim 45 wherein the clocking circuit comprises a shift register.

48. The memory device of claim 45 wherein the clocking circuit comprises a counter latch.

49. The memory device of claim 45 wherein the one logic level comprises a logic one logic level.

50. The memory device of claim 45 wherein the clocking circuit comprises a circuit that clocks on transitions of the first clock signal to a logic one logic level in response to receiving the steady state voltage on the output line.

51. The memory device of claim 45 wherein the clocking circuit comprises a circuit that clocks on only transitions of the first clock signal to a logic zero logic level in response to receiving the steady state voltage on the output line.

52. The memory device of claim 45 wherein the steady state voltage comprises a positive voltage.

53. The memory device of claim 45 wherein the steady state voltage comprises zero volts.

54. The memory device of claim 45 wherein the switching circuit comprises a switching element.

55. The memory device of claim 45 wherein the switching circuit comprises an antifuse.

56. The memory device of claim 45 wherein the switching circuit comprises a transistor.

57. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and

a memory device coupled to the processor through the processor bus, the memory device comprising:

a memory array circuit comprising a plurality of memory cells arranged in rows and columns, a plurality of row lines, and at least one digit for each column of memory cells; and

an addressing circuit coupled to an address bus and the memory array circuit, the addressing circuit adapted to receive row and column addresses on the address bus and activate a corresponding memory cell in the array responsive to a command word, the addressing circuit having a data rate control circuit, the data rate control circuit comprising:

a first clock line receiving a first clock signal that transitions between a pair of logic levels, the first clock signal having a first frequency and a first phase;

a second clock line receiving a second clock signal, the second clock signal having the first frequency and a second phase;

a switching circuit coupled to the second clock line to receive the second clock signal, the switching circuit operative in a first mode to couple the second clock line to an output line, and operative in a second mode to couple a steady state voltage to the output line; and

a clocking circuit coupled to the first clock line and the output line, the clocking circuit structured to clock on transitions of the first clock signal to both logic levels in response to receiving the second clock signal on the output line, and clocking on transitions of the first clock signal to only one logic level in response to receiving the steady state voltage on the output line.

58. The computer system of claim 57 wherein the clocking circuit comprises a circuit that performs a predetermined function each time the clocking circuit clocks.

59. The computer system of claim 57 wherein the clocking circuit comprises a shift register.

60. The computer system of claim 57 wherein the clocking circuit comprises a counter latch.

61. The computer system of claim 57 wherein the one logic level comprises a logic one logic level.

62. The computer system of claim 57 wherein the clocking circuit comprises a circuit that clocks on transitions of the first clock signal to a logic one logic level in response to receiving the steady state voltage on the output line.

63. The computer system of claim 57 wherein the clocking circuit comprises a circuit that clocks on only transitions of the first clock signal to a logic zero logic level in response to receiving the steady state voltage on the output line.

64. The computer system of claim 57 wherein the steady state voltage comprises a positive voltage.

65. The computer system of claim 57 wherein the steady state voltage

comprises zero volts.

66. The computer system of claim 57 wherein the switching circuit comprises a switching element.

67. The computer system of claim 57 wherein the switching circuit comprises an antifuse.

68. The computer system of claim 57 wherein the switching circuit comprises a transistor.

69. A method for controlling the data rate through a clocking circuit, the method comprising the steps of:

providing a first clock signal to the clocking circuit, the first clock signal having a first frequency, a first phase, a first edge, and a second edge;

in a first mode, providing a second clock signal to the clocking circuit, the second clock signal having the first frequency and a second phase;

in a second mode, providing a steady state signal to the clocking circuit;

clocking on a first edge and a second edge of a first clock signal when the second clock signal is provided to the clocking circuit; and

clocking on only one edge of the first clock signal when the steady state signal is provided to the clocking circuit.

TECHNICAL FIELD

This invention relates generally to clocking circuits and more particularly, to a method and apparatus for controlling the data rate of a clocking circuit.

BACKGROUND OF THE INVENTION

Communications between electrical circuits generally require that the circuit receiving the data must be able to receive the data at the same rate and time that the sending circuit transmits it. Discrepancies in the data rate or time of communication between the two circuits can lead to errors or loss of data.

Clocking circuits have traditionally operated at one of two classes of data rates: a single data rate, clocking on one edge of a primary clock, or a double data rate, clocking on both edges of the primary clock. This results in three types of circuits: a circuit that clocks on the rising edge of the primary clock, a circuit that clocks on the falling edge, or a circuit that clocks on both rising and falling edges.

Problems can arise when a circuit of one type tries to communicate with a circuit of another type. In one situation, the transmitting circuit attempts to transfer data at a different rate than the receiving circuit can handle, such as a double data rate processor circuit transmitting to a single data rate SDRAM. When the transmitting circuit transfers data at a faster rate than the receiving circuit can handle, the receiving circuit can miss portions of the data. For example, if a transmitting circuit transmits data at a rate of 66 MHz, while the receiving circuit receives data at 33 MHz, the receiving circuit will at best receive half of the data transmitted (rate of data received/rate of data sent=33 MHz/66 MHz=1/2).

In another situation, the receiving circuit may only "read" the data at a given point in time, and for a given duration. If the data is not present during that time, it may not be received. Here, the transmitting circuit may transmit data on one edge of the primary clock, such as the rising edge, while the receiving circuit "reads" the data on the other edge of

the clock, such as the falling edge.

One solution to this problem is the addition of a latch circuit between the transmitting circuit and the receiving circuit. A latch maintains a data signal until it is overwritten by a new data signal. Thus, data can be held until the receiving circuit is ready to "read" it. The problem with this solution is that this requires additional circuitry; circuitry that takes up space and requires additional power. This is the antithesis of the goals of modern circuit design, which is to minimize the amount of circuitry and power usage.

These problems are particularly prevalent for communications in a synchronous dynamic random access memory (SDRAM). A SDRAM can use all or some of the three clocking protocols discussed above: clocking on the rising edge of a clock signal, the falling edge, or both edges. Similarly, a processor, or more specifically, a memory controller, that communicates with and controls the SDRAM can use all or some of the same three clocking protocols. In order for a given SDRAM to efficiently communicate with a given memory controller, the two circuits must use the same clocking protocol, sending and receiving data at the same rate and time, i.e., both clocking on the same edge or edges of the same clock signal. Thus, the need to match clocking protocols limits the memory controllers that can be used with a given SDRAM.

In the past, proper communication between a given memory controller and the SDRAM has been ensured by producing several types of SDRAMs, each of which uses a single clocking protocol. This solution, however, requires that several different types of SDRAMs and compatible memory controllers be available, and results in an unnecessarily expanded product line by manufacturers and sellers of SDRAMs and memory controllers.

Therefore, there is a need for a single SDRAM or clocking circuit that is capable of operating on either or both edges of a clock signal, for communications with memory controllers having varying data rates and times of communication.

SUMMARY OF THE INVENTION

The present invention provides a method and apparatus for producing a programmable clocking circuit that is capable of operating at either a single data rate or a double data rate and on either the rising or falling edge of a clock signal. A single data rate circuit is a circuit that clocks once per clock cycle, typically on only one edge of a clock signal (rising or falling), while a double data rate circuit clocks twice per clock cycle, typically on both edges (rising and falling) of a clock signal. The double data rate circuit clocks twice as often as the single data rate circuit, hence the name. According to one embodiment of the invention, a clocking circuit receives a first clock signal, and a switching circuit receives a second clock signal. The switching circuit is programmable to couple either the first clock signal to the clocking circuit or a steady state voltage to the clocking circuit. The clocking circuit is structured to clock on the transitions of the first clock signal to both logic levels, typically a logic zero and logic one, in response to receiving the second clock signal from the switching circuit, and clocking on the transition of the first clock signal to only one logic level in response to receiving the steady state voltage from the switching circuit. The data rate and time for communication for the clocking circuit can then be selected by programming the switching circuit to either couple the second clock signal or the steady state voltage to the clocking circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1. is a functional block diagram of a data rate control circuit in accordance with one embodiment of the invention.

FIG. 2A is a schematic diagram of an embodiment of the switching circuit shown in FIG. 1.

FIG. 2B is a schematic diagram of another embodiment of the switching circuit shown in FIG. 1.

FIG. 2C is a schematic diagram of another embodiment of the switching circuit shown in FIG. 1.

FIG. 2D is a schematic diagram of another embodiment of the switching circuit shown in FIG. 1.

FIG. 2E is a schematic diagram of another embodiment of the switching circuit shown in FIG. 1.

FIG. 3 is a functional block diagram of another embodiment of a data rate control circuit in accordance with the invention.

FIG. 4 is a functional block diagram showing the data rate control circuit of FIG. 1 used in a memory device command buffer.

FIG. 5 is a logic diagram of one of the shift register circuits used in the command buffer shown in FIG. 4.

FIG. 6 is a schematic and logic diagram of a shift register stage used in the shift register circuit of FIG. 5.

FIG. 7 is a timing diagram showing various signals present in the shift register of FIG. 6 when operating in a double data rate mode.

FIG. 8 is another timing diagram showing various signals present in the shift register of FIG. 6 when operating in a single data rate mode.

FIG. 9. is a block diagram of a packetized DRAM using the command buffer shown in FIGS. 4-6.

FIG. 10 is a block diagram showing the packetized DRAM of FIG. 9 used in a computer system.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a functional block diagram of an embodiment of the data rate control circuit 10 in accordance with the invention. The data rate control circuit 10 includes a clocking circuit 12, a first clock line 14, a second clock line 16, a switching circuit 18, and a first output line 20. The clocking circuit 12 receives a first clock signal that transitions between two logic levels, such as a logic zero and a logic one, on the first clock line 14. The first clock signal has a first frequency and a first phase. The switching circuit 18 receives a second clock signal having the first frequency and a second phase on the second clock line 16. Typically the second clock signal is a quadrature clock, being 90 degrees out of phase with the first clock signal.

The switching circuit 18 operates in two modes, a first mode where the switching circuit 18 couples the second clock signal to the clocking circuit 12 through the first output line 20, and a second mode where the switching circuit 18 couples a steady state voltage to the clocking circuit 12 through the first output line 20. The clocking circuit 12 clocks on transitions of the first clock signal to both logic levels when the clocking circuit 12 receives the second clock signal from the switching circuit 18, and clocks on transitions of the first clock signal to only one logic level when the clocking circuit 12 receives the steady state voltage from the switching circuit 18. The steady state voltage that is applied on the first output line 20 to the clocking circuit 12 is typically a positive voltage, such as V.sub.cc, but may also be 0 volts, ground, or any other suitable voltage.

In one embodiment, the clocking circuit 12 may be a circuit that performs a predetermined function each time the clocking circuit 12 clocks, such as a shift register shown in FIG. 7 of U.S. patent application No. 08/813,041, which is incorporated herein by reference. The clocking circuit may also be a counter latch, or one of many other circuits known by those skilled in the art. Accordingly, the clocking circuit 12 may produce an output signal on a clocking output line 21 responsive to receiving an input signal on a clocking input line 23.

In another embodiment, when the steady state voltage is applied on the first output line 20 to the clocking circuit 12, the clocking circuit 12 clocks on transitions of the first clock signal to a logic one logic level. The steady state voltage is typically a relatively high voltage, such as a logic one, or V.sub.cc. In another embodiment, the clocking circuit 12 clocks on only transitions of the first clock signal to a logic zero logic level in response to receiving the steady state voltage on the first output line 20. The steady state voltage is typically a relatively low voltage, such as a logic zero, or ground.

Thus, the data rate control circuit 10 functions as a double data rate circuit when the clocking circuit 12 receives the second clock signal on the first output line 20, and a single data rate circuit when the clocking circuit 12 receives the steady state voltage on the first output line 20. When acting as a single data rate circuit, the data rate control circuit 10 is programmable to clock on the transition of the first clock signal to a relatively high voltage by using a relatively high steady state voltage, and is programmable to clock on the transition of the first clock signal to a relatively low voltage by using a relatively low steady state voltage.

In one embodiment of the switching circuit 18, the switching circuit 18 is made up of a switching element that is selectively programmable to couple the steady state voltage source to the first output line 20. This can be accomplished with a switch 22 placed between the steady state voltage source and the first output line 20 as shown in FIG. 2A. This embodiment relies on the voltage from the steady state voltage source to bias the first output line 20 to the steady state voltage, despite the second clock signal that is already present on the first output line 20. Methods for accomplishing this are known to those skilled in the art. Alternately, a switch 24 can be such as shown in FIG. 2B, having two positions, one connected to the second clock line 16 and one connected to the steady state voltage, with the switch 24 decoupling the first output line 20 from the position that the switch 24 is not coupled to.

Similarly, an antifuse 26, as shown in FIG. 2C, may be used to couple the steady state voltage to the first output line 20. The antifuse 26 is placed between the steady state voltage and the first output line 20. By blowing the antifuse 26, the steady state voltage supply is coupled to the first output line 20. Again, this configuration requires the steady state voltage to bias the output line 20 despite the second clock signal which is also present on the first output line 20. Alternately, as shown in FIG. 2D, a fuse 28 or other decoupling device may be placed between the second clock line 16 and the output line 20, and the fuse 28 can be blown in conjunction with blowing the antifuse 26 such that the steady state voltage is coupled to the first output line 20 by the blown antifuse 26, and the second clock signal that is present on the second clock line 16 is decoupled from the first output line 20 by the blown fuse 28. Those skilled in the art will recognize that other methods can be used to decouple the second clock signal from the first output line 20.

In another embodiment of the switching circuit 18, shown in FIG. 2E, a transistor 30 may be placed with its input terminal connected to the steady state voltage source, its output terminal connected to the output line 20, and its control terminal selectively enabled or disabled, thereby coupling or decoupling the steady state voltage from the output line 20. The second clock line 16 can be decoupled from the output line 20 when the steady state voltage is coupled to the output line 20 by the methods described above, or by other methods that are well known in the art,.

In an alternate embodiment of the data rate control circuit 10 shown in FIG. 1, a duty cycle changing circuit 32 may be substituted for the switching circuit 18. In this embodiment the clocking circuit 12 clocks on both edges of the first clock signal in response to receiving a signal on the output line 20 having a first duty cycle, typically 50%, and clocks only one edge of the first clock signal in response to receiving a signal on the output line 20 having a second duty cycle, typically 100% or 0%.

In this embodiment, the first and second clock signals each have a rising edge and a falling edge, and the clocking circuit 12 clocks on only the rising edge of the first clock signal in response to receiving a signal on the output line 20 having the second duty cycle, typically 100%. This results in a single data rate circuit clocking on only the rising edge of the primary clock. Alternately, the clocking circuit 12 can clock on the falling edge of the first clock signal in response to receiving a signal on the output line 20 having the second duty cycle, typically 0%. This results in a single data rate circuit clocking on only the falling edge of the primary circuit.

In both of these embodiments when the clocking circuit 12 receives a signal on the output line 20 having the first duty cycle, the clocking circuit 12 clocks on both the rising and falling edges of the first clock signal, causing the clocking circuit 12 to function as a double data rate circuit. These embodiments function similarly to the embodiment shown in FIG. 1 in most other ways, and may be implemented as shown in FIGS. 2a-e and described above. Further explanation is omitted in the interest of brevity.

Another embodiment of the data rate control circuit 10 uses a frequency changing circuit 34 in place of the switching circuit 18. In this embodiment, the clocking circuit clocks on both edges of the first clock signal in response to receiving a signal on the output line 20 having a first frequency, and clocks on only one edge of the first clock signal in response to receiving a signal on the output line 20 having a second frequency. Typically, the second clock signal has the first frequency, and the voltage source has the second frequency.

In this embodiment, the first frequency is typically a positive number, and the second frequency is typically zero. As in the embodiment with the duty cycle changing circuit described above, the first and second clock signals have first edges and second edges, which can be rising and falling edges.

Thus, the clocking circuit 12 can be programmed with the use of the frequency changing circuit to clock on only the rising edge of the first clock signal in response to receivin