A shared counter performs multiple counting functions in an electronic circuit, such as a memory integrated circuit. An input selection circuit selects one of M input data sets at a given time to be provided as counter initialization data. A counter circuit provides counter output data based on the counter initialization data. An output circuit provides the counter output data to K destination circuits in the electronic circuit. The output circuit provides only one of the K destination circuits with the counter output data at a given time.
The counter circuit comprises the initial value single port RAM having N initial value registers allocated for memorizing N initial values, the counter register single port RAM having N counter registers allocated for memorizing N counting values, and the control circuit for performing a counting operation for each counter register. The control circuit performs the counting operation for each counter register on a time division basis by using a single arithmetic unit.
It is an object of the present invention to make it possible to optionally configure various types of electronic counters. Therefore, the present invention is provided with a one-chip microcomputer 12 having a built-in ROM 13 and RAM 14 to write data corresponding to a variable on a program input through a communication port 10 and an interface 11 in the RAM 14.
A system and method for performing counting operations for a plurality of components is disclosed. A memory stores a plurality of counts from different components. The memory is coupled to a counter and the plurality of counts are accessible to the adder for adding addends to the plurality of counts. A count engine controls the adding of the addends to the plurality of counts.
A buffering circuit of a semiconductor memory device is provided with a plurality of buffers divided into groups, comprising: a first controller for generating a first enable signal in response to a refresh signal and a clock enable signal; a second controller for generating a second enable signal in response to an auto-refresh signal and the first enable signal; a first buffer block including at least one of signal input buffers controlled by the first enable signal; and a second buffer block including at least one of signal input buffers controlled by the second enable signal. The groups of the buffers are independently assigned to their corresponding enable signals.
A memory device includes a memory array, an external clock terminal, and control logic. The memory array is arranged in rows and columns. The external clock terminal is adapted to receive an external clock signal. The external clock signal has at least a first cycle and a second cycle. The first cycle includes a first edge and the second cycle includes a second edge. The control logic is coupled to the memory array and the external clock terminal and adapted to write to a first plurality of the columns in a specified row during the first and second cycles. The control logic is further adapted to suspend the external clock signal to suppress the second edge of the second cycle while writing to the first plurality of the columns. A method for accessing a memory device arranged in rows and columns is provided. The method includes receiving an external clock signal. The external clock signal has at least a first cycle and a second cycle. The first cycle includes a first edge and the second cycle includes a second edge. A first plurality of columns in a specified row are written to during the first and second cycles. The external clock signal is suspended to suppress the second edge of the second cycle while writing to the first plurality of the columns.
