A digital to anologue converter comprises a plurality of current sources (T.sub.o -T.sub.n) and corresponding selection switches (D.sub.o -D.sub.n) which connect the current sources to an output (3). In order to enable a constant capacitance to be presented at the output (3) regardless of the input digital code a plurality of dummy current sources (T.sub.o -T.sub.n) which take the same form as the current sources (To-T.sub.n) are provided. The dummy current sources have associated selection switches ( D.sub.o -D.sub.n) which are operated by the logical inverse of the code applied to the current sources (T.sub.o -T.sub.n).
A new system and method for high-speed testing of semiconductor devices is disclosed. The system utilizes bi-directional FET switches to hide the delay related to the distance signals have to travel between the test head electronics and the device under test. The effect is to increase the frequency with which a prior art tester can test a device. By placing the FET switches closer to the device under test, the device operates on the tester in the same electrical environment as it would in actual use. The device under test can be switched from receiving an input signal to driving an output signal in less time than the TL delay between the test head electronics and the device under test.
A digital to analog converter having low power consumption is provided which includes a reference bias voltage generator for generating a predetermined bias voltage, and a conversion current generator having a plurality of current generators for supplying current which correspond to the bias voltage and a plurality of digital signals to an output terminal.
A digital to analog converter including a first current source (3) to which a first digital signal (28,31) is applied for conversion to an analog signal, wherein the first digital signal has a predetermined clock cycle. The digital to analog converter further comprising a second dummy current source (30) associated with the first current source to which a second digital signal (29,32) is applied. The second digital signal is derived from the first digital signal so that in any one clock cycle either the first or the second current source switches. This arrangement has the advantage that the dynamic behavior of the converter is not signal dependent, but dependent only on the clock cycle.
