An improved method is provided for integrating HSQ into integrated circuit structures and processes, especially those requiring multiple levels of interconnect lines. In a preferred embodiment, interconnect lines 14 are first patterned and etched on a substrate 10. A low-k material such as hydrogen silsesquioxane (HSQ) 18 is spun across the surface of the wafer to fill areas between interconnect lines. A capping layer such as SiO.sub.2 20 is applied to on top of the low-k material. The HSQ is then heated to cure. A thick SiO.sub.2 planarization layer 22 may then be applied and planarized. In other embodiments, the HSQ and SiO.sub.2 process steps can be repeated for multiple layers of HSQ.
CROSS-REFERENCES TO RELATED APPLICATIONS
This application claims priority under 35 U.S.C. .sctn.119(e)(1) of provisional application No. 60/023,133, filed Jul. 30, 1996.
The following co-assigned previously filed applications are related to the instant application and are incorporated herein by reference.
Method and apparatus for using a silylating agent after exposure to an oxidizing environment for repairing damage to low-k dielectric films are described. Plasma photoresist removal, or ashing, may damage bonds in the low-k materials, which may lead to a significant increase in the dielectric constant of the materials. The silylating agent may be used to repair damage to the low-k films after the ashing process. Additionally, a curing process using an oxidizing environment may damage bonds in low-k materials, which may subsequently be repaired by a silylating process. The described method and apparatus may be used with low-k dielectric films including hydrophobic porous oxide films. A chamber for processing a wafer in an oxidizing environment and subsequently performing a silylation process includes an oxidizing agent inlet and a silylating agent inlet. Additionally, a chamber for performing an etch process, processing a wafer in an oxidizing environment, and subsequently performing a silylation process includes an oxidizing agent inlet, a silylating agent inlet, and an etch gas inlet. A cluster tool can include a chamber for processing a wafer in an oxidizing environment and subsequently performing a silylation process, a wafer in/out module, and may include additional processing modules such as etch modules, deposition modules for depositing low-k layers, and deposition modules for depositing cap layers.
Trench isolation structure includes a first conformal insulating film (preferably consisting of silicon nitride) which lines a trench etched in a silicon substrate, an insulating layer (preferably consisting of silicon dioxide) which caps the lined trench and thereby forms a cavity, and a gas (preferably consisting of carbon dioxide) within the cavity. Fabrication of the trench isolation structure is begun by depositing a first conformal insulating film onto the surface of a trench etched in a silicon substrate, thereby forming a lined trench. An amorphous carbon layer is deposited within the lined trench and the lined trench is capped by an insulating layer which encloses the amorphous carbon within a cavity. The solid amorphous carbon within the cavity is converted to carbon dioxide gas by annealing the substrate in an oxidizing ambient. Planarizing the insulating layer to the level of the substrate completes fabrication of the trench isolation structure.
After a MOS type transistor is formed on the surface of a semiconductor substrate, an interlayer insulating film covering the transistor is formed. The insulating film includes a silicon oxide film made of hydrogen silsesquioxane resin in a ceramic state. After a wiring layer is formed on the insulating film, a silicon oxide film as a surface protection film is formed on the insulating film, covering the wiring layer. In order to reduce process damages, heat treatment is performed 30 minutes at 400.degree. C. in a nitrogen gas atmosphere. With this heat treatment, hydrogen in the silicon oxide film is released and diffuses into the channel region of the transistor to lower interfacial energy levels. Since the silicon nitride film does not transmit hydrogen, it is not necessary for the heat treatment atmosphere to contain hydrogen. A variation in threshold voltages of MOS type transistors can be easily lowered.
A new method of forming a non-shrinkable metal passivation layer that will eliminate metal voiding and improve electromigration lifetime of the integrated circuit device is described. Semiconductor device structures are provided in and on a semiconductor substrate and covered by an insulating layer. A metal layer is deposited overlying the insulating layer and patterned to form metal lines wherein there is a gap between two of the metal lines. A non-shrinkable passivation layer is formed according to the following steps: 1) a HDP-CVD oxide layer is deposited overlying the metal lines wherein the gap is filled by the HDP-CVD oxide layer. 2) A silicon nitride layer is deposited by plasma-enhanced chemical vapor deposition overlying the HDP-CVD oxide layer. Or, 1) a PECVD oxide layer is deposited over the metal lines. 2) A silicon nitride layer is deposited by PECVD over the oxide layer to fill the gap and complete the passivation. Then, the fabrication of the integrated circuit device is completed. Completion of fabrication includes thermal processing. Voids are not formed within the metal lines because the non-shrinkable passivation layer does not shrink during the thermal processing.
A semiconductor device with a multilevel interconnection has hydrogen silsesquioxane films which are made porous by etching action of hydrogen fluoride or by ion-implantation of impurities containing fluorine, as an interlayer insulating film for filling up a space between wires. Consequently, a dielectric constant of HSQ is low and wiring capacitance of the multilayer interconnection can be reduced.
