Method for fabricating semiconductor components using focused laser beam

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FIELD OF THE INVENTION

This invention relates generally to semiconductor manufacture, and specifically to a method for fabricating semiconductor components such as packages, interconnects, and test carriers, using a focused laser.

BACKGROUND OF THE INVENTION

As used herein, the term "semiconductor component" refers to an electronic component that includes a semiconductor die, or that makes electrical connections to a semiconductor die. Exemplary semiconductor components include semiconductor packages, multi chip modules, wafers, interconnects, and test carriers for testing dice and packages.

Conventional semiconductor components include external contacts that allow electrical connections to be made from the outside to the integrated circuits contained in the component. For example, semiconductor packages can include external contacts such as solder balls, formed in a ball grid array (BGA) on a substrate of the component.

Besides the external contacts, semiconductor components can also include internal contacts formed on different surfaces of the substrates than the external contacts. For example, semiconductor packages can include bond pads for wire bonding to the dice contained in the packages. Typically, the bond pads are located on a first surface of the package, and the external contacts are located on a second surface of the package. As another example, test carriers for testing semiconductor components, such as bare dice, and chip scale packages, include internal contacts for making temporary electrical connections to the external contacts on components being tested. In addition, the test carriers include external contacts such as pins or balls for making electrical connections to a test board and test circuitry.

With each component electrical paths must be provided through the component, for electrically interconnecting the external contacts to the internal contacts. One method for providing the electrical paths is by forming vias between the contacts, and then filling the vias with a conductive material. For component substrates formed of an etchable material, such as silicon or ceramic, the vias are typically etched in the substrate using a wet or dry etchant. For substrates formed of plastic, such as a glass filled resin (e.g., FR-4), the vias are typically molded, or machined in the substrate.

One problem with interconnecting contacts on semiconductor components is that with advances in semiconductor manufacture, the size and spacing of the contacts is decreasing, and the total number of contacts on a single component is increasing. A chip scale package, for example, can include a hundred, or more, external contacts each having a diameter of only about 10 mils, and a pitch of only about 30 mils.

Interconnecting small, densely spaced, contacts on semiconductor components requires small, densely spaced conductive vias. Because of their small size it can be difficult to fill the vias with a conductive material. Also because of the required size and spacing of the contacts, complex electrical paths must sometimes be provided through the component. Signal delays and high resistivity can result from complex electrical paths.

Furthermore, the conductive vias must sometimes be electrically connected to the contacts using a bonding technique, such as soldering, or wire bonding. The small size of the contacts and vias makes the bonding process difficult. For example, bonding solder balls to metal filled vias can be made difficult by the small size of the solder balls and vias. In a similar manner wire bonding to metal filled vias can be difficult.

The present invention is directed to an improved method for fabricating semiconductor components with small, closely spaced contacts.

SUMMARY OF THE INVENTION

In accordance with the present invention, an improved method for fabricating semiconductor components is provided. Also provided are improved semiconductor components fabricated using the method, including packages, interconnects and test carriers.

The method, simply stated, comprises laser machining conductive vias for interconnecting contacts on a component, using a laser beam that is focused to produce a desired via geometry. An hour glass geometry is produced by focusing the laser beam proximate to a midpoint of the via. The hour glass geometry includes enlarged end portions having increased surface areas for depositing a conductive material into the via, and for forming contacts on the via. An inwardly tapered geometry is produced by focusing the laser beam proximate to an exit point of the beam from the substrate. An outwardly tapered geometry is produced by focusing the laser beam proximate to an entry point of the beam into the substrate.

Following laser machining, the via is at least partially filled with a conductive material such as a metal or conductive polymer. In addition, the conductive material can include contacts on either end, or the contacts can "fan out" on a surface of the substrate. In addition, external contacts such as balls or pins, can be formed on the contacts using a bonding technique such as wire bonding, soldering or adhesive bonding.

In a first embodiment of the method, a semiconductor package is fabricated. The package includes a substrate, and a semiconductor die flip chip mounted to the substrate. The substrate includes conductive vias having first contacts on a first surface of the substrate, and second contacts on a second opposing surface of the substrate. Bumped bond pads on the die are bonded to the first contacts, and contact balls for making outside electrical connections to the package are bonded to the second contacts.

In a second embodiment of the method, a test carrier for testing semiconductor components, such as chip scale packages and bare dice, is provided. The carrier comprises a base, conductive vias in the base, and first and second contacts on either side of the conductive vias for making temporary electrical connections between a component under test, and test circuitry of a test apparatus (e.g., burn-in board). The first contacts on the conductive vias comprise conductive pockets for electrically engaging external contacts (e.g., solder balls) on the component under test. The second contacts on the conductive vias comprise pads, and contact pins are bonded to the pads, for electrically engage mating electrical connectors on the test apparatus.

In a third embodiment of the method, an interconnect for testing a semiconductor wafer is fabricated. The interconnect includes a substrate, conductive vias in the substrate, and first and second contacts on either side of the conductive vias for making temporary electrical connections between the wafer and test circuitry. Contact pins are bonded to the first contacts, and are adapted to electrically engage bond pads on dice contained on the wafer. The contact pins comprise wires bonded to the first contacts, and formed in a compliant shape, such as a spring segment.

The second contacts on the interconnect comprise pads for electrically engaging spring loaded electrical connectors (e.g., POGO PINS) of the test circuitry.

The method of the invention, generally stated, includes the steps of: providing a substrate for a component having a first surface and a second surface; laser machining an opening in substrate from the first surface to the second surface using a laser beam; selecting a focal point of the laser beam to form the opening with at least one enlarged end portion; depositing a conductive material through the enlarged end portion into the opening to form a conductive via; and forming a contact on the enlarged end portion.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a side elevation view of a semiconductor package constructed in accordance with the invention;

FIG. 1B is a bottom view of the package taken along section line 1B--1B of FIG. 1A;

FIG. 1C is a cross sectional view of the package taken along section line

1C--1C of FIG. 1B;

FIG. 1D is an enlarged view of a portion of FIG. 1C taken along section line 1D showing a conductive via and contacts on the conductive via;

FIG. 1E is an enlarged view equivalent to FIG. 1D of an alternate embodiment conductive via;

FIG. 1F is an enlarged view equivalent to FIG. 1D of an alternate embodiment conductive via;

FIGS. 2A-2D are schematic cross sectional views illustrating process steps for fabricating the conductive vias for the package shown in FIGS. 1A-1D;

FIG. 2E is a bottom view of the conductive via taken along section line 2E--2E of FIG. 2D illustrating a contact thereon;

FIG. 2F is a schematic cross sectional view of an alternate embodiment conductive via;

FIG. 2G is a bottom view of the alternate embodiment conductive via taken along section line 2G--2G of FIG. 2F illustrating an alternate embodiment contact thereon;

FIG. 3 is a schematic cross sectional view illustrating alternate embodiment conductive vias;

FIG. 4 is a schematic cross sectional view illustrating alternate embodiment conductive vias;

FIG. 4A is a bottom view of the alternate embodiment conductive vias taken along section line 4A--4A of FIG. 4;

FIG. 5A is an exploded schematic perspective view of a test carrier constructed in accordance with the invention;

FIG. 5B is a schematic perspective view of the assembled test carrier of FIG. 5A;

FIG. 5C is an enlarged schematic cross sectional view taken along section line 5C--5C of FIG. 5A;

FIGS. 6A-6F are schematic cross sectional views illustrating process steps in a method for fabricating the test carrier of FIGS. 5A-5C;

FIG. 7 is a schematic plan view of an interconnect constructed in accordance wi