A preloadable floating point unit includes first and second preload registers that hold a next operand and a next top of array (TOA) for use with a next FPU instruction held in an instruction queue pending completion of the current FPU instruction.
A method and apparatus for improving the performance of a superscalar, superpipelined processor by identifying and processing instructions for performing addressing operations is provided. The invention heuristically determines instructions likely to perform addressing operations and assigns those instructions to specialized pipes in a pipeline structure. The invention can assign such instructions to both an execute pipe and a load/store pipe to avoid the occurrence of "bubbles" in the event execution of the instruction requires the calculation capability of the execute pipe. The invention can also examine a sequence of instructions to identify an instruction for performing a calculation where the result of the calculation is used by a succeeding load or store instruction. In this case, the invention controls the pipeline to assure the result of the calculation is available for the succeeding load or store instruction even if both instructions are being processed concurrently.
A method and apparatus for improving the performance of a superscalar, superpipelined processor by identifying and processing instructions for performing addressing operations is provided. The invention heuristically determines instructions likely to perform addressing operations and assigns those instructions to specialized pipes in a pipeline structure. The invention can assign such instructions to both an execute pipe and a load/store pipe to avoid the occurrence of "bubbles" in the event execution of the instruction requires the calculation capability of the execute pipe. The invention can also examine a sequence of instructions to identify an instruction for performing a calculation where the result of the calculation is used by a succeeding load or store instruction. In this case, the invention controls the pipeline to assure the result of the calculation is available for the succeeding load or store instruction even if both instructions are being processed concurrently.
The present invention relates to data processing systems with built-in error recovery from a given checkpoint. In order to checkpoint more than one instruction per cycle it is proposed to collect updates of a predetermined maximum number of register contents performed by a respective plurality of CISC/RISC instructions in a buffer (CSB)(60) for checkpoint states, whereby a checkpoint state comprises as many buffer slots as registers can be updated by said plurality of CISC instructions and an entry for a Program Counter value associated with the youngest external instruction of said plurality, and to update an Architected Register Array (ARA)(64) with freshly collected register data after determining that no error was detected in the register data after completion of said youngest external instruction of said plurality of external instructions. Handshake synchronization for consistent updates between storage in an L2-cache (66) via a Store Buffer (65) and an Architected Register Array (ARA) (64) is provided which is based on the youngest instruction ID (40) stored in the Checkpoint State Buffer (CSB) (60).
A method (and structure) of linear algebra processing, including processing a matrix data of a triangular packed format matrix in at least one matrix subroutine designed to process matrix data in a full format, using a hybrid full-packed data structure that provides a rectangular data structure for the triangular packed data.
A method (and structure) for improving at least one of speed and efficiency when executing level 3 dense linear algebra subroutines on a computer. An optimal matrix subroutine is selected from among a plurality of matrix subroutines stored in a memory that could alternatively perform a level 3 matrix multiplication or factorization processing.
