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| United States Patent | 6115836 |
| Link to this page | http://www.wikipatents.com/6115836.html |
| Inventor(s) | Churchill; Jonathan F. (Reading, GB), Raftery; Neil P. (Guildford, GB), Hendry; Colin J. (South Maidenhead, GB), Shanmugam; Jeyakumar (San Jose, CA), Finn; Mark A. (Mountain View, CA), Surrette; Thomas M. (Saratoga, CA), Phelan; Cathal G. (Mountain View, CA), Pancholy; Ashish (Milpitas, CA) |
| Abstract | A circuit for generating a pulse including a scan register having a first
scan bit; first logic device receiving a first signal and generating a
second signal; and a programmable delay circuit coupled to the scan
register and the first logic device. The programmable delay circuit
receives the second signal and generates a delayed second signal after a
programmable period of time. The programmable period of time is determined
by the first scan bit. The circuit also includes a logic circuit that
recevies the second signal and the delayed second signal. The logic
circuiit outputs the pulse having a pulse width proportional to the
programmable period of time. |
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Title Information  |
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Drawing from US Patent 6115836 |
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Scan path circuitry for programming a variable clock pulse width |
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| Inventor |
Churchill; Jonathan F. (Reading, GB) , Raftery; Neil P. (Guildford, GB) , Hendry; Colin J. (South Maidenhead, GB) , Shanmugam; Jeyakumar (San Jose, CA) , Finn; Mark A. (Mountain View, CA) , Surrette; Thomas M. (Saratoga, CA) , Phelan; Cathal G. (Mountain View, CA) , Pancholy; Ashish (Milpitas, CA) |
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| Publication Date |
September 5, 2000 |
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| Filing Date |
September 17, 1997 |
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| Parent Case |
CROSS-REFERENCE TO RELATED APPLICATIONS
This application may be related to U.S. patent application Ser. No.
08/932,315 entitled "SCAN PATH CIRCUITRY INCLUDING A PROGRAMMABLE DELAY
CIRCUIT" (attorney docket no. 16820.P214), now U.S. Pat. No. 5,936,977,
U.S. patent application Ser. No. 08/932,638 entitled "SCAN PATH CIRCUITRY
INCLUDING AN OUTPUT REGISTER HAVING A FLOW THROUGH MODE" (attorney docket
no. 16820.P215), now U.S. Pat. No. 5,953,285, and U.S. patent application
Ser. No. 08/932,637 entitled "TEST MODE FEATURES FOR SYNCHRONOUS AND
PIPELINED MEMORIES" (attorney docket no. 16820.P201) now U.S. Pat. No.
6,006,347. |
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Title Information |
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