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Apparatus for testing a fixed logic value interconnection between integrated circuits
   
Document Number
US Patent 6119256
Issued Date
September 12, 2000
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Abstract
A device which includes a first integrated circuit and a second IC for applying a fixed logic value to an input of the first integrated circuit. A conventional implementation uses pull-up and pull-down resistors, but these resistors necessitate an additional step and additional elements for the testing of the relevant interconnections. The device is improved in that an output of the second IC, which outputs the logic value during normal operation, is controlled via test logic during testing. As a result, the interconnections between the output of the second IC and the input of the first IC are tested in the same way and as part of the testing of the other interconnections between the first and second integrated circuits.
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Apparatus for testing a fixed logic value interconnection between integrated circuits - US Patent 6119256 Drawing
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Number of Claims:
17
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Owner
Published
September 12, 2000
Application Number
08/356,946
Filed
December 15, 1994
US Classification
714/726   714/30
Int'l Classification
G06F   11/267   (20060101)   G01R   31/28   (20060101)   G01R   31/3185   (20060101)  
Examiner
Attorney/Law Firm
Priority Data
Dec 16, 1993 [EP] 93203547
USPTO Field of Search
371/22.3   371/22.1   371/22.5   371/22.2   371/25.1   324/158.1   324/73.1   714/5   714/8   714/25   714/26   714/30   714/32   714/43   714/726   714/729   714/733   714/735   365/201  
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