A control voltage is supplied from a phase locked loop (PLL), which includes a phase detector and a voltage controlled oscillator (VCO), to a delay circuit. The VCO is made up of a plurality of inverters connected together in a ring. The control voltage is also supplied to each of these inverters so as to control an oscillation frequency of the VCO. The control voltage is defined based on a phase difference between a reference clock signal and an oscillation clock signal. The delay circuit is made up of a plurality of inverters connected in series to each other. A delay caused by each of these inverters is controlled with the same voltage as the control voltage. A serial signal is input to an initial-stage one of the inverters. A latch circuit latches the output signals of the respective inverters of the delay circuit in response to a latch clock signal, which has been generated by dividing the frequency of the reference clock signal. And based on a result of latching, a parallel signal is output.

A method for use in a data transmission system comprises the steps of: (i) adding timing information to a serial data stream; (ii) recovering the timing information from the serial data stream to generate a plurality of clock signals associated with the timing information, each clock signal having a common frequency and a different phase associated therewith, the common frequency being less than a frequency associated with the serial data stream; and (iii) converting the serial data stream to a plurality of parallel data streams respectively using the plurality of clock signals. The timing information may be added to the serial data stream at a data transmitter portion of the system. The invention provides for various ways to add the timing information to the serial data stream, i.e., enrich the serial data stream with the timing information. This timing information is preferably phase locked to the data and has a frequency less than the serial data transmission rate. Recovery of this lower speed timing information, e.g., clock tones, may be performed via filtering and phase aligning the timing information to generate the plurality of clock signals. Conversion of the serial data stream to the plurality of parallel data streams may then include using the clock signals to respectively sample or de-multiplex the serial data stream to yield the plurality of parallel data streams. The parallel data streams have a clock rate lower than that associated with the received serial data stream.

A serializer serializes N data (N>2) in N stages into a serial data stream. Each stage includes a logic section and a first inverter. The logic section receives i-th data (where i is less than or equal to N) of the N parallel data to output the i-th data or inverted i-th data in response to an active status or an inactive status of an j-th clock signal (where j is less than or equal to N) of the N clock signals. The first inverter receives the i-th data or the inverted i-th data from the logic section and inverts the i-th data or the inverted i-th data to output a first output signal. The output signal of the serializer may have reduced jitter even when the serializer operates in a high speed and a low power condition.

An integrated circuit can operate in a first mode as a parallel-to-serial converter, and in a second mode as a serial-to-parallel converter. Some of the components of the integrated circuit are used in both modes. For example, the IC has a single parallel interface, which is used as a parallel input in the first mode, and as a parallel output in the second mode. Further, the IC includes a single phase-locked loop circuit, which is used in a clock multiplier unit in the first mode, and in a clock recovery circuit in the second mode.

A transmission interface compatible with the AT Attachment Packet Interface (ATAPI) that achieves transfer rates greater than those possible with an Integrated Disc Electronics (IDE) bus. The transmission interface includes a transmission ATAPI circuit, a packetizing circuit and a converter. The transmission ATAPI circuit monitors the content of the ATAPI and, when a change is detected, generates a first set of signals representative of that change. The first set of signals are single-ended, parallel to one another and use Transistor-Transistor Logic (TTL) voltage levels. The packetizing circuit packetizes the first set of signals to generate a second set of signals, which representing a packet. The packet payload represents the change in the contents of the ATAPI. The second set of signals are also single-ended, parallel to one another and use TTL voltage levels. The converter converts the second set of signals into a third set of signals and couples these to a serial bus. The third set of signals are serial to one another, and use low voltage level, differential signaling. Thus, the third set of signal are suited for transmission by the serial bus, which includes many fewer wires than available in an IDE bus while operating at a faster data rate.