Method and apparatus for fabricating contacts to substrate regions through a low k, low density dielectric. A cap is formed over gates and side spacers are formed along the edges of the gates so as to surround the gates in a relatively dense (e.g., silicon dioxide) insulative material. A low k or low density layer of a polymer or silica aerogel or xerogel material is formed in contact with the substrate covering the gate structures including the spacers. An unlanded contact opening is etched through the low k, low density dielectric with an etchant that provides high selectivity between the insulation surrounding the gate and the low k, low density layer.
RELATED APPLICATIONS
This application is related to co-pending applications Ser. No. 829,054, filed Apr. 28, 1997, entitled "A Method to Fabricate Unlanded Vias with a Low Dielectric Constant Material as an Intraline Dielectric"; and Ser. No. 829,112, filed Mar. 31, 1997, entitled "A Novel Damascene Interconnect Structure to Achieve Unlanded Vias for Low k Materials"; both assigned to the Assignee of the present application.
The present invention describes methods, apparatus, and systems related to polysilicon gate contact openings over active regions formed by a separate mask to provide enough control of dielectric removal to produce a contact opening at least down to the gate layer but not down to the junction layers. Embodiments include, self-aligned polysilicon contacts done by timed contact etch, by a two layer dielectric, by adding a dielectric etch stop layer, and by partially planarizing a dielectric or etch stop layer over the gate layer. Thus, even if misaligned, the gate contact openings will be deep enough to reach active region gates, but not deep enough to reach junctions. As a result, by using a separate mask and by selecting a period of time for etching to active gates, gate contact openings can be formed during manufacture of ICs, semiconductors, MOS memory cells, SRAM, flash memory, and various other memory cells.
Disclosed is a process for removing doped silicon dioxide from a structure selectively to undoped silicon dioxide. A structure having both doped and undoped silicon dioxide regions is exposed to a high density plasma etch having a fluorinated etch chemistry. Doped silicon dioxide is preferably removed thereby at a rate 10 times or more greater than that of undoped silicon dioxide. The etch is conducted in a chamber having an upper electrode to which a source power is applied and a lower electrode to which a bias power is applied sufficient to generate a power density on a surface of the structure such that the source power density is in a range less than or equal to about 1000 W per 200-mm diameter wafer surface. The high density plasma etch has an ion density not less that about 10.sup.9 ions/cm.sup.3. A variety of structures are formed with the etch process, including self-aligned contacts to a semiconductor substrate.
A MOSFET structure and method of fabricating the structure incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. The multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. Alternatively, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. The multi-layer spacer may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.
The present invention describes methods, apparatus, and systems related to polysilicon gate contact openings over active regions formed by a separate mask to provide enough control of dielectric removal to produce a contact opening at least down to the gate layer but not down to the junction layers. Embodiments include, self-aligned polysilicon contacts done by timed contact etch, by a two layer dielectric, by adding a dielectric etch stop layer, and by partially planarizing a dielectric or etch stop layer over the gate layer. Thus, even if mis-aligned, the gate contact openings will be deep enough to reach active region gates, but not deep enough to reach junctions. As a result, by using a separate mask and by selecting a period of time for etching to active gates, gate contact openings can be formed during manufacture of ICs, semiconductors, MOS memory cells, SRAM, flash memory, and various other memory cells.
The present invention describes methods, apparatus, and systems related to polysilicon gate contact openings over active regions formed by a separate mask to provide enough control of dielectric removal to produce a contact opening at least down to the gate layer but not down to the junction layers. Embodiments include, self-aligned polysilicon contacts done by timed contact etch, by a two layer dielectric, by adding a dielectric etch stop layer, and by partially planarizing a dielectric or etch stop layer over the gate layer. Thus, even if mis-aligned, the gate contact openings will be deep enough to reach active region gates, but not deep enough to reach junctions. As a result, by using a separate mask and by selecting a period of time for etching to active gates, gate contact openings can be formed during manufacture of ICs, semiconductors, MOS memory cells, SRAM, flash memory, and various other memory cells.
