A multi-scale shuffle is used in the generation of orthogonal and pseudo-orthogonal codes. A method for generating a family of pseudo-random orthogonal or pseudo-orthogonal code signals, comprises the steps of (1) generating a seed matrix of original dimensions, (2) performing a plurality of expansions on the seed matrix, each successive expansion producing a next generation matrix of larger dimensions, the last of the expansions including replication and shuffling of a parent generation matrix to produce a child generation matrix, and (3) output row of the final matrix as the family code signals. The shuffling may comprise a pseudo-random re-ordering of matrix column indices. The replication and shuffling may comprise forming a child generation matrix by operations that include combining a reproduction of the parent matrix and a shuffled reproduction of the parent matrix. The replication and shuffling also may comprise forming an intermediate matrix by operations that include combining a reproduction of the parent matrix, a modified reproduction of the parent matrix, a shuffled reproduction of the parent matrix, and a modified shuffled reproduction of the parent matrix, and then shuffling the intermediate matrix to form the child matrix.
A controllable bit stream generator for providing a random bit source with a desired probability. The controllable bit stream generator comprises a digital component which generates a pseudo-random bit sequence, a variable probability conditioner coupled to the digital component and which accepts the pseudo-random bit sequence and outputs a corresponding controlled output, and a register coupled to the variable probability conditioner. The register is utilized to send a control signal to the variable probability conditioner. The controllable bit stream generator creates a random output bit sequence for the controlled output utilizing the variable probability conditioner and the control signal of the register.
A system for run-time verification of operations within a logic structure of a digital system. The system comprises of a controllable bit stream generator for simulating an occurrence of a data travelling through said logic structure at a desired time. It also comprises of means for selecting a characteristic of the data where the characteristic includes how to verify the logic structure, and means for verifying the logic structure utilizing a combination of a controlled bit stream output of the controllable bit stream generator and the characteristic of the data.
Quasi-Walsh function systems are developed which allow multiple access as well as spectral spreading for interception and jamming prevention. Mutual interference is minimal due to orthogonal spreading. High signal hiding capability occurs by utilizing a large number of distinct orthogonal codes. An encoding algorithm is presented which allows a simple way of "keeping track" of the different systems of Quasi-Walsh systems as well as determining appropriate values for given users at specified chip values.
In some pseudo-orthogonal waveform embodiments, a radar system transmits pseudo-orthogonal waveforms and performs multiple correlations on a combined single receiver channel signal. In some quadratic polyphase waveform embodiments, a radar system may simultaneously transmit frequency separated versions of a single quadratic polyphase waveform on a plurality of transmit antennas, combine the return signal from each antenna into a combined time-domain signal, and perform a Fourier transformation on the combined time-domain signal to locate a target. The radar system may identify a target, such as sniper's bullet, incoming projectile, rocket-propelled grenade (RPG) or a mortar shell. In some embodiments, the system may estimate the target's trajectory to intercept the target. In some embodiments, the system may estimate the target's trajectory and may further extrapolate the target's trajectory to locate the target's source, such as the sniper.
A system for controllable run-time verification of operations in a logic structure of a digital system. The system comprises a controllable bit stream generator which produces a controlled bit stream output. The controlled bit stream output corresponds to a bit sequence which instantiates a verification of operations within the logic structure. The system also comprises means for coupling the controlled bit stream output to the logic structure to verify the operations of the logic structure.
